From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org, iii@linux.ibm.com
Subject: [PATCH v2 30/33] target/arm: Change gen_jmp* to work on displacements
Date: Tue, 16 Aug 2022 15:33:57 -0500 [thread overview]
Message-ID: <20220816203400.161187-31-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220816203400.161187-1-richard.henderson@linaro.org>
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 35 ++++++++++++++++++++---------------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 63a41ed438..4d13e365e2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -270,6 +270,12 @@ static uint32_t read_pc(DisasContext *s)
return s->pc_curr + (s->thumb ? 4 : 8);
}
+/* The pc_curr difference for an architectural jump. */
+static int jmp_diff(DisasContext *s, int diff)
+{
+ return diff + (s->thumb ? 4 : 8);
+}
+
/* Set a variable to the value of a CPU register. */
void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
{
@@ -2614,10 +2620,8 @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
}
/* Jump, specifying which TB number to use if we gen_goto_tb() */
-static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
+static void gen_jmp_tb(DisasContext *s, int diff, int tbno)
{
- int diff = dest - s->pc_curr;
-
if (unlikely(s->ss_active)) {
/* An indirect jump so that we still trigger the debug exception. */
gen_update_pc(s, diff);
@@ -2659,9 +2663,9 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
}
}
-static inline void gen_jmp(DisasContext *s, uint32_t dest)
+static inline void gen_jmp(DisasContext *s, int diff)
{
- gen_jmp_tb(s, dest, 0);
+ gen_jmp_tb(s, diff, 0);
}
static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
@@ -8331,7 +8335,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
static bool trans_B(DisasContext *s, arg_i *a)
{
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
@@ -8346,14 +8350,14 @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a)
return true;
}
arm_skip_unless(s, a->cond);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
static bool trans_BL(DisasContext *s, arg_i *a)
{
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
@@ -8373,7 +8377,8 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
}
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
store_cpu_field_constant(!s->thumb, thumb);
- gen_jmp(s, (read_pc(s) & ~3) + a->imm);
+ /* This difference computes a page offset so ok for TARGET_TB_PCREL. */
+ gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm);
return true;
}
@@ -8534,10 +8539,10 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
* when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
*/
}
- gen_jmp_tb(s, s->base.pc_next, 1);
+ gen_jmp_tb(s, curr_insn_len(s), 1);
gen_set_label(nextlabel);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
@@ -8617,7 +8622,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
if (a->f) {
/* Loop-forever: just jump back to the loop start */
- gen_jmp(s, read_pc(s) - a->imm);
+ gen_jmp(s, jmp_diff(s, -a->imm));
return true;
}
@@ -8648,7 +8653,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
tcg_temp_free_i32(decr);
}
/* Jump back to the loop start */
- gen_jmp(s, read_pc(s) - a->imm);
+ gen_jmp(s, jmp_diff(s, -a->imm));
gen_set_label(loopend);
if (a->tp) {
@@ -8656,7 +8661,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
}
/* End TB, continuing to following insn */
- gen_jmp_tb(s, s->base.pc_next, 1);
+ gen_jmp_tb(s, curr_insn_len(s), 1);
return true;
}
@@ -8755,7 +8760,7 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE,
tmp, 0, s->condlabel);
tcg_temp_free_i32(tmp);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
--
2.34.1
next prev parent reply other threads:[~2022-08-16 21:16 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-16 20:33 [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Richard Henderson
2022-08-16 20:33 ` [PATCH v2 01/33] linux-user/arm: Mark the commpage executable Richard Henderson
2022-08-16 20:33 ` [PATCH v2 02/33] linux-user/hppa: Allocate page zero as a commpage Richard Henderson
2022-08-16 20:33 ` [PATCH v2 03/33] linux-user/x86_64: Allocate vsyscall page " Richard Henderson
2022-08-17 11:50 ` Ilya Leoshkevich
2022-08-16 20:33 ` [PATCH v2 04/33] linux-user: Honor PT_GNU_STACK Richard Henderson
2022-08-16 20:33 ` [PATCH v2 05/33] tests/tcg/i386: Move smc_code2 to an executable section Richard Henderson
2022-08-16 20:33 ` [PATCH v2 06/33] accel/tcg: Remove PageDesc code_bitmap Richard Henderson
2022-08-16 20:33 ` [PATCH v2 07/33] accel/tcg: Use bool for page_find_alloc Richard Henderson
2022-08-16 20:33 ` [PATCH v2 08/33] accel/tcg: Make tb_htable_lookup static Richard Henderson
2022-08-16 20:33 ` [PATCH v2 09/33] accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c Richard Henderson
2022-08-16 20:33 ` [PATCH v2 10/33] accel/tcg: Properly implement get_page_addr_code for user-only Richard Henderson
2022-08-16 20:33 ` [PATCH v2 11/33] accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostp Richard Henderson
2022-08-16 20:33 ` [PATCH v2 12/33] accel/tcg: Add nofault parameter to get_page_addr_code_hostp Richard Henderson
2022-08-16 20:33 ` [PATCH v2 13/33] accel/tcg: Unlock mmap_lock after longjmp Richard Henderson
2022-08-16 20:33 ` [PATCH v2 14/33] accel/tcg: Raise PROT_EXEC exception early Richard Henderson
2022-08-16 20:33 ` [PATCH v2 15/33] accel/tcg: Introduce is_same_page() Richard Henderson
2022-08-16 20:33 ` [PATCH v2 16/33] accel/tcg: Remove translator_ldsw Richard Henderson
2022-08-16 20:33 ` [PATCH v2 17/33] accel/tcg: Add pc and host_pc params to gen_intermediate_code Richard Henderson
2022-08-16 20:33 ` [PATCH v2 18/33] accel/tcg: Add fast path for translator_ld* Richard Henderson
2022-08-16 20:33 ` [PATCH v2 19/33] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Richard Henderson
2022-08-16 20:33 ` [PATCH v2 20/33] accel/tcg: Do not align tb->page_addr[0] Richard Henderson
2022-08-16 20:33 ` [PATCH v2 21/33] include/hw/core: Create struct CPUJumpCache Richard Henderson
2022-08-16 20:33 ` [PATCH v2 22/33] accel/tcg: Introduce tb_pc and tb_pc_log Richard Henderson
2022-08-16 20:33 ` [PATCH v2 23/33] accel/tcg: Introduce TARGET_TB_PCREL Richard Henderson
2022-08-16 20:33 ` [PATCH v2 24/33] accel/tcg: Split log_cpu_exec into inline and slow path Richard Henderson
2022-08-16 20:33 ` [PATCH v2 25/33] target/arm: Introduce curr_insn_len Richard Henderson
2022-08-16 20:33 ` [PATCH v2 26/33] target/arm: Change gen_goto_tb to work on displacements Richard Henderson
2022-08-16 20:33 ` [PATCH v2 27/33] target/arm: Change gen_*set_pc_im to gen_*update_pc Richard Henderson
2022-08-16 20:33 ` [PATCH v2 28/33] target/arm: Change gen_exception_insn* to work on displacements Richard Henderson
2022-08-16 20:33 ` [PATCH v2 29/33] target/arm: Change gen_exception_internal " Richard Henderson
2022-08-16 20:33 ` Richard Henderson [this message]
2022-08-16 20:33 ` [PATCH v2 31/33] target/arm: Introduce gen_pc_plus_diff for aarch64 Richard Henderson
2022-08-16 20:33 ` [PATCH v2 32/33] target/arm: Introduce gen_pc_plus_diff for aarch32 Richard Henderson
2022-08-16 20:34 ` [PATCH v2 33/33] target/arm: Enable TARGET_TB_PCREL Richard Henderson
2022-08-16 20:41 ` Richard Henderson
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