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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id e2sm12451698wrt.8.2021.10.25.13.57.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Oct 2021 13:57:01 -0700 (PDT) Message-ID: <21b998e6-f915-a96b-0802-41156b4db76a@amsat.org> Date: Mon, 25 Oct 2021 22:57:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH] hvf: arm: Ignore cache operations on MMIO Content-Language: en-US To: Alexander Graf , Cameron Esfahani References: <20211025191349.52992-1-agraf@csgraf.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20211025191349.52992-1-agraf@csgraf.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-2.846, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kettenis@openbsd.org, qemu-devel@nongnu.org, AJ Barris , Roman Bolshakov , Paolo Bonzini , osy@github.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/25/21 21:13, Alexander Graf wrote: > Apple's Hypervisor.Framework forwards cache operations as MMIO traps > into user space. For MMIO however, these have no meaning: There is no > cache attached to them. > > So let's filter SYS instructions for DATA exits out and treat them as nops. > > This fixes OpenBSD booting as guest. > > Signed-off-by: Alexander Graf > Reported-by: AJ Barris > --- > target/arm/hvf/hvf.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c > index bff3e0cde7..46ff4892a7 100644 > --- a/target/arm/hvf/hvf.c > +++ b/target/arm/hvf/hvf.c > @@ -1098,6 +1098,33 @@ static void hvf_sync_vtimer(CPUState *cpu) > } > } > > +static bool hvf_emulate_insn(CPUState *cpu) > +{ > + ARMCPU *arm_cpu = ARM_CPU(cpu); > + CPUARMState *env = &arm_cpu->env; > + uint32_t insn; > + > + /* > + * We ran into an instruction that traps for data, but is not > + * hardware predecoded. This should not ever happen for well > + * behaved guests. Let's try to see if we can somehow rescue > + * the situation. > + */ > + > + cpu_synchronize_state(cpu); > + if (cpu_memory_rw_debug(cpu, env->pc, &insn, 4, 0)) { What about using cpu_ldl_data()? > + /* Could not read the instruction */ > + return false; > + } > + > + if ((insn & 0xffc00000) == 0xd5000000) { Could there be an endianess issue here? Otherwise, Reviewed-by: Philippe Mathieu-Daudé > + /* MSR/MRS/SYS/SYSL - happens for cache ops which are nops on data */ > + return true; > + } > + > + return false; > +} > + > int hvf_vcpu_exec(CPUState *cpu) > { > ARMCPU *arm_cpu = ARM_CPU(cpu); > @@ -1156,6 +1183,11 @@ int hvf_vcpu_exec(CPUState *cpu) > hvf_exit->exception.physical_address, isv, > iswrite, s1ptw, len, srt); > > + if (!isv) { > + g_assert(hvf_emulate_insn(cpu)); > + advance_pc = true; > + break; > + } > assert(isv); > > if (iswrite) { >