From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Delevoryas <me@pjd.dev>
Cc: <peter.maydell@linaro.org>, <andrew@aj.id.au>, <joel@jms.id.au>,
<cminyard@mvista.com>, <titusr@google.com>,
<qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>, <zhdaniel@fb.com>,
<pdel@fb.com>
Subject: Re: [PATCH v3 14/14] hw/arm/aspeed: Add oby35-cl machine
Date: Thu, 30 Jun 2022 13:02:54 +0200 [thread overview]
Message-ID: <24f848a7-3b3e-9125-bedd-dedc1460a8f0@kaod.org> (raw)
In-Reply-To: <20220630045133.32251-15-me@pjd.dev>
On 6/30/22 06:51, Peter Delevoryas wrote:
> From: Peter Delevoryas <pdel@fb.com>
>
> The fby35 machine includes 4 server boards, each of which has a "bridge
> interconnect" (BIC). This chip abstracts the pinout for the server board
> into a single endpoint that the baseboard management controller (BMC)
> can talk to using IPMB.
>
> This commit adds a machine for testing the BIC on the server board. It
> runs OpenBIC (https://github.com/facebook/openbic) and the server board
> is called CraterLake, so the code name is oby35-cl. There's also a
> variant of the baseboard that replaces the BMC with a BIC, but that
> machine is not included here.
>
> A test image can be built from https://github.com/facebook/openbic using
> the instructions in the README.md to build the meta-facebook/yv35-cl
> recipe, or retrieved from my Github:
>
> wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.17.01/Y35BCL.elf
>
> And you can run this machine with the following command:
>
> qemu-system-arm -machine oby35-cl -nographic -kernel Y35BCL.elf
>
> It should produce output like the following:
>
> [00:00:00.005,000] <inf> usb_dc_aspeed: select ep[0x81] as IN endpoint
> [00:00:00.006,000] <inf> usb_dc_aspeed: select ep[0x82] as IN endpoint
> [00:00:00.006,000] <wrn> usb_dc_aspeed: pre-selected ep[0x1] as IN endpoint
> [00:00:00.006,000] <wrn> usb_dc_aspeed: pre-selected ep[0x2] as IN endpoint
> [00:00:00.006,000] <inf> usb_dc_aspeed: select ep[0x3] as OUT endpoint
> *** Booting Zephyr OS build v00.01.05 ***
> Hello, welcome to yv35 craterlake 2022.25.1
> BIC class type(class-1), 1ou present status(0), 2ou present status(0), board revision(0x1)
> check_vr_type: i2c4 0x62 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x62 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x62 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x62 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x76 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 0 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> check_vr_type: i2c4 0x60 page 1 [04 00 81 d2 49 3c ff ff ff ff ff ff ff ff ff ff]
> [init_drive_type] sensor 0x14 post sensor read failed!
>
> [init_drive_type] sensor 0x30 post sensor read failed!
> [init_drive_type] sensor 0x39 post sensor read failed!
> ipmi_init
> [set_DC_status] gpio number(15) status(0)
> [set_post_status] gpio number(1) status(1)
> uart:~$ [00:00:01.010,000] <inf> kcs_aspeed: KCS3: addr=0xca2, idr=0x2c, odr=0x38, str=0x44
>
> [00:00:01.016,000] <err> spi_nor_multi_dev: [1216][spi1_cs0]SFDP magic 00000000 invalid
> [00:00:01.016,000] <err> spi_nor_multi_dev: [1456]SFDP read failed: -22
> [00:00:01.010,000] <inf> kcs_aspeed: KCS3: addr=0xca2, idr=0x2c, odr=0x38, str=0x44
>
> [00:00:01.016,000] <err> spi_nor_multi_dev: [1216][spi1_cs0]SFDP magic 00000000 invalid
> [00:00:01.016,000] <err> spi_nor_multi_dev: [1456]SFDP read failed: -22
> uart:~$ BIC Ready
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
LGTM.
That said I would prefer to introduce the machine first and then
populate with devices.
May be it is time to introduce a new machine file. This one seems
like it could go in a f35.c file, also because a larger f35-* is
in plan. aspeed.c could contain the basic definitions and helpers.
> ---
> hw/arm/aspeed.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index a06f7c1b62..75971ef2ca 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1429,6 +1429,50 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
> amc->macs_mask = 0;
> }
>
> +static void oby35_cl_i2c_init(AspeedMachineState *bmc)
> +{
> + AspeedSoCState *soc = &bmc->soc;
> + I2CBus *i2c[14];
> + I2CBus *ssd[8];
> + int i;
> +
> + for (i = 0; i < 14; i++) {
> + i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
> + }
> + get_pca9548_channels(i2c[1], 0x71, ssd);
We should rename to aspeed_get_pca9548_channels
> +
> + i2c_slave_create_simple(i2c[0], "fby35-sb-cpld", 0x21);
> + i2c_slave_create_simple(i2c[1], "tmp105", 0x48);
> + i2c_slave_create_simple(i2c[1], "tmp105", 0x49);
> + i2c_slave_create_simple(i2c[1], "tmp105", 0x4a);
> + i2c_slave_create_simple(i2c[1], "adm1272", 0x40);
> + i2c_slave_create_simple(i2c[1], "tmp421", 0x4c);
> + i2c_slave_create_simple(i2c[2], "intel-me", 0x16);
> + i2c_slave_create_simple(i2c[4], "isl69259", 0x76);
> + i2c_slave_create_simple(i2c[4], "isl69259", 0x62);
> + i2c_slave_create_simple(i2c[4], "isl69259", 0x60);
> +
> + for (int i = 0; i < 8; i++) {
> + i2c_slave_create_simple(ssd[i], "tmp105", 0x6a);
> + }
> +
> + /*
> + * FIXME: This should actually be the BMC, but both the ME and the BMC
QEMU has an embedded IPMI BMC simulator.
> + * are IPMB endpoints, and the current ME implementation is generic
> + * enough to respond normally to some things.
> + */
> + i2c_slave_create_simple(i2c[6], "intel-me", 0x10);
> +}
> +
> +static void aspeed_machine_oby35_cl_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> +
> + mc->desc = "Meta Platforms fby35 CraterLake BIC (Cortex-M4)";
> + amc->i2c_init = oby35_cl_i2c_init;
> +}
> +
> static const TypeInfo aspeed_machine_types[] = {
> {
> .name = MACHINE_TYPE_NAME("palmetto-bmc"),
> @@ -1494,6 +1538,10 @@ static const TypeInfo aspeed_machine_types[] = {
> .name = MACHINE_TYPE_NAME("ast1030-evb"),
> .parent = TYPE_ASPEED_MACHINE,
> .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
> + }, {
> + .name = MACHINE_TYPE_NAME("oby35-cl"),
> + .parent = MACHINE_TYPE_NAME("ast1030-evb"),
hmm, so we are inheriting from the evb ?
C.
> + .class_init = aspeed_machine_oby35_cl_class_init,
> }, {
> .name = TYPE_ASPEED_MACHINE,
> .parent = TYPE_MACHINE,
next prev parent reply other threads:[~2022-06-30 11:06 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-30 4:51 [PATCH v3 00/14] hw/i2c/aspeed: I2C slave mode DMA RX w/ new regs Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 01/14] hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 02/14] hw/i2c/aspeed: Fix DMA len write-enable bit handling Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 03/14] hw/i2c/aspeed: Fix MASTER_EN missing error message Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 04/14] hw/i2c: support multiple masters Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 05/14] hw/i2c: add asynchronous send Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 06/14] hw/i2c/aspeed: add slave device in old register mode Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 07/14] hw/i2c/aspeed: Add new-registers DMA slave mode RX support Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 08/14] hw/i2c/pmbus: Add idle state to return 0xff's Peter Delevoryas
2022-06-30 19:18 ` Titus Rwantare
2022-06-30 4:51 ` [PATCH v3 09/14] hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators Peter Delevoryas
2022-06-30 19:20 ` Titus Rwantare
2022-06-30 4:51 ` [PATCH v3 10/14] hw/sensor: Add Renesas ISL69259 device model Peter Delevoryas
2022-06-30 6:30 ` Cédric Le Goater
2022-06-30 19:16 ` Titus Rwantare
2022-07-01 5:35 ` Cédric Le Goater
2022-06-30 19:16 ` Titus Rwantare
2022-06-30 21:14 ` Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 11/14] hw/misc/aspeed: Add PECI controller Peter Delevoryas
2022-06-30 6:32 ` Cédric Le Goater
2022-06-30 4:51 ` [PATCH v3 12/14] hw/misc/aspeed: Add fby35-sb-cpld Peter Delevoryas
2022-06-30 6:47 ` Cédric Le Goater
2022-06-30 4:51 ` [PATCH v3 13/14] hw/misc/aspeed: Add intel-me Peter Delevoryas
2022-06-30 11:09 ` Cédric Le Goater
2022-06-30 16:20 ` Peter Delevoryas
2022-06-30 4:51 ` [PATCH v3 14/14] hw/arm/aspeed: Add oby35-cl machine Peter Delevoryas
2022-06-30 11:02 ` Cédric Le Goater [this message]
2022-06-30 16:15 ` Peter Delevoryas
2022-06-30 16:42 ` Cédric Le Goater
2022-06-30 17:48 ` Peter Delevoryas
2022-06-30 23:06 ` Peter Delevoryas
2022-07-01 5:39 ` Cédric Le Goater
2022-06-30 6:13 ` [PATCH v3 00/14] hw/i2c/aspeed: I2C slave mode DMA RX w/ new regs Cédric Le Goater
2022-06-30 7:50 ` Cédric Le Goater
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