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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id e12sm19457469wrn.56.2019.12.15.16.17.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 15 Dec 2019 16:17:33 -0800 (PST) Subject: Re: [PATCH 05/10] arm: allwinner-h3: add System Control module To: Niek Linnenbank References: <20191202210947.3603-1-nieklinnenbank@gmail.com> <20191202210947.3603-6-nieklinnenbank@gmail.com> <949aec5f-fd92-9fb2-25f4-803cd1bbf601@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <25c838e3-af9a-d742-6946-056c431a8805@redhat.com> Date: Mon, 16 Dec 2019 01:17:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: tzER5Wl6M0uC09yRGQWsHQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/16/19 12:27 AM, Niek Linnenbank wrote: > On Fri, Dec 13, 2019 at 1:09 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > On 12/2/19 10:09 PM, Niek Linnenbank wrote: [...] > > +static const MemoryRegionOps allwinner_h3_syscon_ops =3D { > > +=C2=A0 =C2=A0 .read =3D allwinner_h3_syscon_read, > > +=C2=A0 =C2=A0 .write =3D allwinner_h3_syscon_write, > > +=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN, > > +=C2=A0 =C2=A0 .valid =3D { > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 4, > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4, >=20 > Can you point me to the datasheet page that says this region is > restricted to 32-bit accesses? Maybe you want .valid -> .impl instead= ? >=20 > Hehe well here I can only give the same answer as for the SD/MMC driver:= =20 > the datasheet > only provides the base address and register offsets, but nothing=20 > explicitely mentioned about alignment. > I do see that also for this device the registers are 32-bit aligned. >=20 > Does that mean I should change MemoryRegionOps to . impl instead? No, keep them, but add ".impl.min_access_size =3D 4" (see answer to SD/MMC= =20 model patch).