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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch Content-Language: en-US To: Weiwei Li , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com References: <20230327100027.61160-1-liweiwei@iscas.ac.cn> <20230327100027.61160-6-liweiwei@iscas.ac.cn> From: Daniel Henrique Barboza In-Reply-To: <20230327100027.61160-6-liweiwei@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/27/23 07:00, Weiwei Li wrote: > Transform the fetch address before page walk when pointer mask is > enabled for instruction fetch. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu.h | 1 + > target/riscv/cpu_helper.c | 25 +++++++++++++++++++++++-- > target/riscv/csr.c | 2 -- > 3 files changed, 24 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 638e47c75a..57bd9c3279 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -368,6 +368,7 @@ struct CPUArchState { > #endif > target_ulong cur_pmmask; > target_ulong cur_pmbase; > + bool cur_pminsn; > > /* Fields from here on are preserved across CPU reset. */ > QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index f88c503cf4..77132a3e0c 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -124,6 +124,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > void riscv_cpu_update_mask(CPURISCVState *env) > { > target_ulong mask = -1, base = 0; > + bool insn = false; > /* > * TODO: Current RVJ spec does not specify > * how the extension interacts with XLEN. > @@ -135,18 +136,21 @@ void riscv_cpu_update_mask(CPURISCVState *env) > if (env->mmte & M_PM_ENABLE) { > mask = env->mpmmask; > base = env->mpmbase; > + insn = env->mmte & MMTE_M_PM_INSN; > } > break; > case PRV_S: > if (env->mmte & S_PM_ENABLE) { > mask = env->spmmask; > base = env->spmbase; > + insn = env->mmte & MMTE_S_PM_INSN; > } > break; > case PRV_U: > if (env->mmte & U_PM_ENABLE) { > mask = env->upmmask; > base = env->upmbase; > + insn = env->mmte & MMTE_U_PM_INSN; > } > break; > default: > @@ -161,6 +165,7 @@ void riscv_cpu_update_mask(CPURISCVState *env) > env->cur_pmmask = mask; > env->cur_pmbase = base; > } > + env->cur_pminsn = insn; > } > > #ifndef CONFIG_USER_ONLY > @@ -1225,6 +1230,17 @@ static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) > riscv_pmu_incr_ctr(cpu, pmu_event_type); > } > > +static target_ulong adjust_pc_address(CPURISCVState *env, target_ulong pc) > +{ > + target_ulong adjust_pc = pc; > + > + if (env->cur_pminsn) { > + adjust_pc = (adjust_pc & ~env->cur_pmmask) | env->cur_pmbase; > + } > + > + return adjust_pc; > +} > + > bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr) > @@ -1232,6 +1248,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > vaddr im_address; > + vaddr orig_address = address; > hwaddr pa = 0; > int prot, prot2, prot_pmp; > bool pmp_violation = false; > @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", > __func__, address, access_type, mmu_idx); > > + if (access_type == MMU_INST_FETCH) { > + address = adjust_pc_address(env, address); > + } > + > /* MPRV does not affect the virtual-machine load/store > instructions, HLV, HLVX, and HSV. */ > if (riscv_cpu_two_stage_lookup(mmu_idx)) { > @@ -1351,13 +1372,13 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > } > > if (ret == TRANSLATE_SUCCESS) { > - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), > + tlb_set_page(cs, orig_address & ~(tlb_size - 1), pa & ~(tlb_size - 1), > prot, mmu_idx, tlb_size); > return true; > } else if (probe) { > return false; > } else { > - raise_mmu_exception(env, address, access_type, pmp_violation, > + raise_mmu_exception(env, orig_address, access_type, pmp_violation, > first_stage_error, > riscv_cpu_virt_enabled(env) || > riscv_cpu_two_stage_lookup(mmu_idx), > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d522efc0b6..4544c9d934 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3511,8 +3511,6 @@ static RISCVException write_mmte(CPURISCVState *env, int csrno, > /* for machine mode pm.current is hardwired to 1 */ > wpri_val |= MMTE_M_PM_CURRENT; > > - /* hardwiring pm.instruction bit to 0, since it's not supported yet */ > - wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); > env->mmte = wpri_val | PM_EXT_DIRTY; > riscv_cpu_update_mask(env); >