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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id b5sm5616603pfb.190.2020.05.07.11.33.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2020 11:33:44 -0700 (PDT) Subject: Re: [PATCH] linux-user/sparc64: Translate flushw opcode To: LemonBoy , qemu-devel@nongnu.org, laurent@vivier.eu References: <894ec93e-05dd-2110-a0c2-e0afa2fa6fd5@gmail.com> From: Richard Henderson Message-ID: <27e075a8-0ef8-cf17-8153-0bd9354bb744@linaro.org> Date: Thu, 7 May 2020 11:33:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <894ec93e-05dd-2110-a0c2-e0afa2fa6fd5@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/10/20 2:14 PM, LemonBoy wrote: > From 11d0cfe58d12e0f191b435ade88622cfceb2098a Mon Sep 17 00:00:00 2001 > From: LemonBoy > Date: Fri, 10 Apr 2020 22:55:26 +0200 > Subject: [PATCH] linux-user/sparc64: Translate flushw opcode > > The ifdef logic should unconditionally compile in the `xop == 0x2b` case > when targeting sparc64. > > Fix the handling of window spill traps by keeping cansave into account > when calculating the new CWP. This is two separate fixes and should be two separate patches. > bsd-user/main.c | 4 +++- > linux-user/sparc/cpu_loop.c | 4 +++- First patch, > target/sparc/translate.c | 2 ++ > 3 files changed, 8 insertions(+), 2 deletions(-) Second patch. > + /* cansave is zero if the spill trap handler is triggered by `save` and */ > + /* nonzero if triggered by a `flushw` */ Format the comment like so: /* * cansave is zero... * nonzero if ... */ > + save_window_offset(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); But this does match the implementation in sparc_cpu_do_interrupt, so the change is good. > diff --git a/target/sparc/translate.c b/target/sparc/translate.c > index 9416a551cf..1a4efd4ed6 100644 > --- a/target/sparc/translate.c > +++ b/target/sparc/translate.c > @@ -3663,6 +3663,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) > #endif > gen_store_gpr(dc, rd, cpu_tmp0); > break; > +#endif > +#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) > } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ > #ifdef TARGET_SPARC64 > gen_helper_flushw(cpu_env); Look ok here too. r~