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[64.229.69.35]) by smtp.gmail.com with ESMTPSA id c204sm596790qkb.90.2019.09.11.07.40.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Sep 2019 07:40:06 -0700 (PDT) To: David Hildenbrand , qemu-devel@nongnu.org References: <20190906075750.14791-1-david@redhat.com> <20190906075750.14791-3-david@redhat.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <28507e0d-f7b3-74e6-43df-95a53a162e12@linaro.org> Date: Wed, 11 Sep 2019 10:40:04 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190906075750.14791-3-david@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::741 Subject: Re: [Qemu-devel] [PATCH v2 02/28] s390x/tcg: MVCL: Zero out unused bits of address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Weimer , Thomas Huth , Cornelia Huck , Stefano Brivio , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/6/19 3:57 AM, David Hildenbrand wrote: > We have to zero out unused bits in 24 and 31-bit addressing mode. > Provide a new helper. > > Signed-off-by: David Hildenbrand > --- > target/s390x/mem_helper.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson > diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c > index 39ee9b3175..3152bdafe2 100644 > --- a/target/s390x/mem_helper.c > +++ b/target/s390x/mem_helper.c > @@ -469,6 +469,26 @@ static inline uint64_t get_address(CPUS390XState *env, int reg) > return wrap_address(env, env->regs[reg]); > } > > +/* > + * Store the address to the given register, zeroing out unused leftmost > + * bits in bit positions 32-63 (24-bit and 31-bit mode only). > + */ > +static inline void set_address_zero(CPUS390XState *env, int reg, > + uint64_t address) > +{ > + if (env->psw.mask & PSW_MASK_64) { > + env->regs[reg] = address; > + } else { > + if (!(env->psw.mask & PSW_MASK_32)) { > + address &= 0x00ffffff; > + env->regs[reg] = deposit64(env->regs[reg], 0, 32, address); > + } else { > + address &= 0x7fffffff; > + env->regs[reg] = deposit64(env->regs[reg], 0, 32, address); > + } You could perhaps sink the deposit and store line into the outer else. r~