From: "Andrew Jeffery" <andrew@aj.id.au>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-arm@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Ryan Chen" <ryan_chen@aspeedtech.com>,
"Corey Minyard" <minyard@acm.org>,
"Cameron Esfahani via" <qemu-devel@nongnu.org>,
"Joel Stanley" <joel@jms.id.au>,
"Cédric Le Goater" <clg@kaod.org>
Subject: Re: [PATCH 1/4] arm: ast2600: Force a multiple of 32 of IRQs for the GIC
Date: Mon, 01 Mar 2021 10:53:18 +1030 [thread overview]
Message-ID: <2885b969-3386-4d73-b187-d395b253543e@www.fastmail.com> (raw)
In-Reply-To: <10a65ca0-0f6a-46be-a292-d37647e03a7f@www.fastmail.com>
On Mon, 1 Mar 2021, at 09:37, Andrew Jeffery wrote:
>
>
> On Fri, 26 Feb 2021, at 19:26, Philippe Mathieu-Daudé wrote:
> > On 2/26/21 7:57 AM, Andrew Jeffery wrote:
> > > This appears to be a requirement of the GIC model.
> >
> > If so this should be adjusted in the GIC or a15mp_priv_realize(),
> > not in each caller, isn't it?
> >
>
> Maybe, let me look into it. I'll clean it up in v2 if it makes sense.
So the current behaviour has been around since 2009, originating in
41c1e2f54e6f ("arm: make sure that number of irqs can be represented in
GICD_TYPER."). The GIC architecture specification says:
"The GICD_TYPER.ITLinesNumber field identifies the number of
implemented GICD_ISENABLERns, and therefore the maximum number of SPIs
that might be supported."
While the code says:
/* ITLinesNumber is represented as (N / 32) - 1 (see
* gic_dist_readb) so this is an implementation imposed
* restriction, not an architectural one:
*/
if (s->num_irq < 32 || (s->num_irq % 32)) {
error_setg(errp,
"%d interrupt lines unsupported: not divisible by
32",
num_irq);
return;
}
My feeling is that it's better to be explicit in the models that are
affected (i.e. leave the ROUND_UP() as I have it in this patch). This
way if the implementation restriction is ever lifted, we know which
models we can clean up. I won't be reworking the GIC to remove the
restriction in this series, so unless you have a particularly strong
preference/justification for the implicit ROUND_UP(), I plan to leave
it as is.
Cheers,
Andrew
next prev parent reply other threads:[~2021-03-01 0:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 6:57 [PATCH 0/4] aspeed: LPC peripheral controller devices Andrew Jeffery
2021-02-26 6:57 ` [PATCH 1/4] arm: ast2600: Force a multiple of 32 of IRQs for the GIC Andrew Jeffery
2021-02-26 8:56 ` Philippe Mathieu-Daudé
2021-02-28 23:07 ` Andrew Jeffery
2021-03-01 0:23 ` Andrew Jeffery [this message]
2021-02-26 6:57 ` [PATCH 2/4] arm: ast2600: Fix iBT IRQ ID Andrew Jeffery
2021-02-26 8:58 ` Philippe Mathieu-Daudé
2021-02-28 23:08 ` Andrew Jeffery
2021-02-26 6:57 ` [PATCH 3/4] hw/misc: Add a basic Aspeed LPC controller model Andrew Jeffery
2021-02-26 6:57 ` [PATCH 4/4] hw/misc: Model KCS devices in the Aspeed LPC controller Andrew Jeffery
2021-02-26 9:51 ` Cédric Le Goater
2021-02-28 23:14 ` Andrew Jeffery
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