From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.6 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DA0AC433DB for ; Fri, 26 Feb 2021 10:09:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8FF164EC8 for ; Fri, 26 Feb 2021 10:09:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E8FF164EC8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:37394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFa3n-0002Jg-KA for qemu-devel@archiver.kernel.org; Fri, 26 Feb 2021 05:09:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFZtl-00006M-Tp for qemu-devel@nongnu.org; Fri, 26 Feb 2021 04:59:01 -0500 Received: from mx2.suse.de ([195.135.220.15]:51342) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFZtj-0001N5-DS for qemu-devel@nongnu.org; Fri, 26 Feb 2021 04:59:01 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 64C7AAF3F; Fri, 26 Feb 2021 09:58:57 +0000 (UTC) Subject: Re: [PATCH v24 16/18] target/i386: gdbstub: introduce aux functions to read/write CS64 regs To: Paolo Bonzini , Richard Henderson , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Eduardo Habkost , Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= References: <20210226094939.11087-1-cfontana@suse.de> <20210226094939.11087-17-cfontana@suse.de> From: Claudio Fontana Message-ID: <2bee4ef2-4704-a0e3-4fd0-1fe66d8952d7@suse.de> Date: Fri, 26 Feb 2021 10:58:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210226094939.11087-17-cfontana@suse.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.435, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Roman Bolshakov , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/26/21 10:49 AM, Claudio Fontana wrote: > a number of registers are read as 64bit under the condition that > (hflags & HF_CS64_MASK) || TARGET_X86_64) > > and a number of registers are written as 64bit under the condition that > (hflags & HF_CS64_MASK). > > Provide some auxiliary functions that do that. > > Signed-off-by: Claudio Fontana > Cc: Paolo Bonzini > --- > target/i386/gdbstub.c | 155 ++++++++++++++---------------------------- > 1 file changed, 51 insertions(+), 104 deletions(-) > > diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c > index 41e265fc67..4ad1295425 100644 > --- a/target/i386/gdbstub.c > +++ b/target/i386/gdbstub.c > @@ -78,6 +78,23 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; > #define GDB_FORCE_64 0 > #endif > > +static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val) I wonder if this "target_ulong" is actually wrong. Could we have a target "i386" (not TARGET_X86_64) for which HF_CS64_MASK gets set? > +{ > + if ((hflags & HF_CS64_MASK) || GDB_FORCE_64) { > + return gdb_get_reg64(buf, val); > + } > + return gdb_get_reg32(buf, val); > +} > + > +static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val) same here... > +{ > + if (hflags & HF_CS64_MASK) { > + *val = ldq_p(buf); > + return 8; > + } > + *val = ldl_p(buf); > + return 4; > +} > > int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > { > @@ -142,25 +159,14 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > return gdb_get_reg32(mem_buf, env->segs[R_FS].selector); > case IDX_SEG_REGS + 5: > return gdb_get_reg32(mem_buf, env->segs[R_GS].selector); > - > case IDX_SEG_REGS + 6: > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->segs[R_FS].base); > - } > - return gdb_get_reg32(mem_buf, env->segs[R_FS].base); > - > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_FS].base); > case IDX_SEG_REGS + 7: > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->segs[R_GS].base); > - } > - return gdb_get_reg32(mem_buf, env->segs[R_GS].base); > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_GS].base); > > case IDX_SEG_REGS + 8: > #ifdef TARGET_X86_64 > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->kernelgsbase); > - } > - return gdb_get_reg32(mem_buf, env->kernelgsbase); > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->kernelgsbase); > #else > return gdb_get_reg32(mem_buf, 0); > #endif > @@ -188,45 +194,23 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > return gdb_get_reg32(mem_buf, env->mxcsr); > > case IDX_CTL_CR0_REG: > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->cr[0]); > - } > - return gdb_get_reg32(mem_buf, env->cr[0]); > - > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]); > case IDX_CTL_CR2_REG: > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->cr[2]); > - } > - return gdb_get_reg32(mem_buf, env->cr[2]); > - > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[2]); > case IDX_CTL_CR3_REG: > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->cr[3]); > - } > - return gdb_get_reg32(mem_buf, env->cr[3]); > - > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[3]); > case IDX_CTL_CR4_REG: > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->cr[4]); > - } > - return gdb_get_reg32(mem_buf, env->cr[4]); > - > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[4]); > case IDX_CTL_CR8_REG: > -#ifdef CONFIG_SOFTMMU > +#ifndef CONFIG_USER_ONLY > tpr = cpu_get_apic_tpr(cpu->apic_state); > #else > tpr = 0; > #endif > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, tpr); > - } > - return gdb_get_reg32(mem_buf, tpr); > + return gdb_read_reg_cs64(env->hflags, mem_buf, tpr); > > case IDX_CTL_EFER_REG: > - if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) { > - return gdb_get_reg64(mem_buf, env->efer); > - } > - return gdb_get_reg32(mem_buf, env->efer); > + return gdb_read_reg_cs64(env->hflags, mem_buf, env->efer); > } > } > return 0; > @@ -266,7 +250,8 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > { > X86CPU *cpu = X86_CPU(cs); > CPUX86State *env = &cpu->env; > - uint32_t tmp; > + target_ulong tmp; And here. Thanks, Claudio > + int len; > > /* N.B. GDB can't deal with changes in registers or sizes in the middle > of a session. So if we're in 32-bit mode on a 64-bit cpu, still act > @@ -329,30 +314,13 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf); > case IDX_SEG_REGS + 5: > return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf); > - > case IDX_SEG_REGS + 6: > - if (env->hflags & HF_CS64_MASK) { > - env->segs[R_FS].base = ldq_p(mem_buf); > - return 8; > - } > - env->segs[R_FS].base = ldl_p(mem_buf); > - return 4; > - > + return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_FS].base); > case IDX_SEG_REGS + 7: > - if (env->hflags & HF_CS64_MASK) { > - env->segs[R_GS].base = ldq_p(mem_buf); > - return 8; > - } > - env->segs[R_GS].base = ldl_p(mem_buf); > - return 4; > - > + return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_GS].base); > case IDX_SEG_REGS + 8: > #ifdef TARGET_X86_64 > - if (env->hflags & HF_CS64_MASK) { > - env->kernelgsbase = ldq_p(mem_buf); > - return 8; > - } > - env->kernelgsbase = ldl_p(mem_buf); > + return gdb_write_reg_cs64(env->hflags, mem_buf, &env->kernelgsbase); > #endif > return 4; > > @@ -382,57 +350,36 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > return 4; > > case IDX_CTL_CR0_REG: > - if (env->hflags & HF_CS64_MASK) { > - cpu_x86_update_cr0(env, ldq_p(mem_buf)); > - return 8; > - } > - cpu_x86_update_cr0(env, ldl_p(mem_buf)); > - return 4; > + len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); > + cpu_x86_update_cr0(env, tmp); > + return len; > > case IDX_CTL_CR2_REG: > - if (env->hflags & HF_CS64_MASK) { > - env->cr[2] = ldq_p(mem_buf); > - return 8; > - } > - env->cr[2] = ldl_p(mem_buf); > - return 4; > + len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); > + env->cr[2] = tmp; > + return len; > > case IDX_CTL_CR3_REG: > - if (env->hflags & HF_CS64_MASK) { > - cpu_x86_update_cr3(env, ldq_p(mem_buf)); > - return 8; > - } > - cpu_x86_update_cr3(env, ldl_p(mem_buf)); > - return 4; > + len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); > + cpu_x86_update_cr3(env, tmp); > + return len; > > case IDX_CTL_CR4_REG: > - if (env->hflags & HF_CS64_MASK) { > - cpu_x86_update_cr4(env, ldq_p(mem_buf)); > - return 8; > - } > - cpu_x86_update_cr4(env, ldl_p(mem_buf)); > - return 4; > + len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); > + cpu_x86_update_cr4(env, tmp); > + return len; > > case IDX_CTL_CR8_REG: > - if (env->hflags & HF_CS64_MASK) { > -#ifdef CONFIG_SOFTMMU > - cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf)); > + len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); > +#ifndef CONFIG_USER_ONLY > + cpu_set_apic_tpr(cpu->apic_state, tmp); > #endif > - return 8; > - } > -#ifdef CONFIG_SOFTMMU > - cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf)); > -#endif > - return 4; > + return len; > > case IDX_CTL_EFER_REG: > - if (env->hflags & HF_CS64_MASK) { > - cpu_load_efer(env, ldq_p(mem_buf)); > - return 8; > - } > - cpu_load_efer(env, ldl_p(mem_buf)); > - return 4; > - > + len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); > + cpu_load_efer(env, tmp); > + return len; > } > } > /* Unrecognised register. */ >