From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, frederic.petrot@univ-grenoble-alpes.fr,
alistair.francis@wdc.com, fabien.portas@grenoble-inp.org
Subject: Re: [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB
Date: Wed, 13 Oct 2021 16:31:40 +0800 [thread overview]
Message-ID: <2c15a089-c4b8-ecae-287a-94f1e5e9719a@c-sky.com> (raw)
In-Reply-To: <20211007174722.929993-13-richard.henderson@linaro.org>
On 2021/10/8 上午1:47, Richard Henderson wrote:
> The count zeros instructions require a separate implementation
> for RV32 when TARGET_LONG_BITS == 64.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/translate.c | 16 ++++++++++++
> target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++-------------
> 2 files changed, 32 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f960929c16..be458ae0c2 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -510,6 +510,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
> return true;
> }
>
> +static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
> + void (*f_tl)(TCGv, TCGv),
> + void (*f_32)(TCGv, TCGv))
> +{
> + int olen = get_olen(ctx);
> +
> + if (olen != TARGET_LONG_BITS) {
> + if (olen == 32) {
> + f_tl = f_32;
> + } else {
> + g_assert_not_reached();
> + }
> + }
> + return gen_unary(ctx, a, ext, f_tl);
> +}
> +
> static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index c62eea433a..adc35b6491 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1)
> tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> }
>
> +static void gen_clzw(TCGv ret, TCGv arg1)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_shli_tl(t, arg1, 32);
> + tcg_gen_clzi_tl(ret, t, 32);
> + tcg_temp_free(t);
> +}
> +
> static bool trans_clz(DisasContext *ctx, arg_clz *a)
> {
> REQUIRE_ZBB(ctx);
> - return gen_unary(ctx, a, EXT_ZERO, gen_clz);
> + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
> }
>
> static void gen_ctz(TCGv ret, TCGv arg1)
> @@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1)
> tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> }
>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ctzi_tl(ret, ret, 32);
Typo:
tcg_gen_ctzi_tl(ret, arg1, 32);
Otherwise,
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Thanks,
Zhiwei
> +}
> +
> static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> {
> REQUIRE_ZBB(ctx);
> - return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
> + return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
> }
>
> static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
> @@ -314,14 +327,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
> return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
> }
>
> -static void gen_clzw(TCGv ret, TCGv arg1)
> -{
> - TCGv t = tcg_temp_new();
> - tcg_gen_shli_tl(t, arg1, 32);
> - tcg_gen_clzi_tl(ret, t, 32);
> - tcg_temp_free(t);
> -}
> -
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -329,17 +334,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> return gen_unary(ctx, a, EXT_NONE, gen_clzw);
> }
>
> -static void gen_ctzw(TCGv ret, TCGv arg1)
> -{
> - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> - tcg_gen_ctzi_tl(ret, ret, 64);
> -}
> -
> static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
> + return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
> }
>
> static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
next prev parent reply other threads:[~2021-10-13 8:33 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 17:47 [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-07 17:47 ` [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-08 2:28 ` Alistair Francis
2021-10-13 12:13 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-11 23:28 ` Alistair Francis
2021-10-13 12:18 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-07 17:47 ` [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-13 16:46 ` Frédéric Pétrot
2021-10-13 16:54 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-07 17:47 ` [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-07 17:47 ` [PATCH 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-07 17:47 ` [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-07 17:47 ` [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-07 17:47 ` [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 11:54 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-13 11:45 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 8:31 ` LIU Zhiwei [this message]
2021-10-07 17:47 ` [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-13 11:24 ` LIU Zhiwei
2021-10-10 15:17 ` [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Frédéric Pétrot
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