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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id 18sm11471532wmj.28.2020.10.05.00.39.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Oct 2020 00:39:30 -0700 (PDT) Subject: Re: [PATCH 15/16] target/mips/cpu: Do not allow system-mode use without input clock To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Igor Mammedov , Thomas Huth References: <20200928171539.788309-1-f4bug@amsat.org> <20200928171539.788309-16-f4bug@amsat.org> <20200929150154.04f77949@redhat.com> <35db3210-8165-6fe8-c835-22970fb31c93@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <2e1ef61c-688d-0a1d-ae0a-1cc11d555cd4@amsat.org> Date: Mon, 5 Oct 2020 09:39:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <35db3210-8165-6fe8-c835-22970fb31c93@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , Eduardo Habkost , Paul Burton , "Edgar E . Iglesias" , qemu-devel@nongnu.org, Wainer dos Santos Moschetta , Aleksandar Markovic , =?UTF-8?Q?Herv=c3=a9_Poussineau?= , Jiaxun Yang , Cleber Rosa , Huacai Chen , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" +Thomas for qtest On 9/29/20 4:40 PM, Philippe Mathieu-Daudé wrote: > On 9/29/20 3:01 PM, Igor Mammedov wrote: >> On Mon, 28 Sep 2020 19:15:38 +0200 >> Philippe Mathieu-Daudé wrote: >> >>> Now than all QOM users provides the input clock, do not allow >>> using a CPU core without its input clock connected on system-mode >>> emulation. For user-mode, keep providing a fixed 200 MHz clock, >>> as it used by the RDHWR instruction (see commit cdfcad788394). >>> >>> Signed-off-by: Philippe Mathieu-Daudé >>> --- >>> Cc: Igor Mammedov >>> >>> We need the qtest check for tests/qtest/machine-none-test.c >>> which instanciate a CPU with the none machine. Igor, is it >>> better to remove the MIPS targets from the test cpus_map[]? >> >> I don't get idea, could you rephrase/elaborate? > > cpu_class_init sets: > > /* > * Reason: CPUs still need special care by board code: wiring up > * IRQs, adding reset handlers, halting non-first CPUs, ... > */ > dc->user_creatable = false; > > but the CPUs are created via another path in vl.c: > > current_machine->cpu_type = parse_cpu_option(cpu_option); > > The machine-none-test assumes CPU objects are user-creatable. > > With this patch I enforce MIPS CPU to have an input clock > connected, so they are not user-creatable anymore. > > I tried this code ...: > > --- a/target/mips/cpu.c > +++ b/target/mips/cpu.c > @@ -229,7 +229,11 @@ static const TypeInfo mips_cpu_type_info = { > static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) > { > MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); > + DeviceClass *dc = DEVICE_CLASS(oc); > + > mcc->cpu_def = data; > + /* Reason: clock need to be wired up */ > + dc->user_creatable = false; > } > > ... but it is ignored, the CPU can still be created. > > Not sure how to handle this. > >> >>> --- >>> target/mips/cpu.c | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >>> index 2f75216c324..cc4ee75af30 100644 >>> --- a/target/mips/cpu.c >>> +++ b/target/mips/cpu.c >>> @@ -25,6 +25,7 @@ >>> #include "kvm_mips.h" >>> #include "qemu/module.h" >>> #include "sysemu/kvm.h" >>> +#include "sysemu/qtest.h" >>> #include "exec/exec-all.h" >>> #include "hw/qdev-clock.h" >>> #include "hw/qdev-properties.h" >>> @@ -159,11 +160,18 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) >>> Error *local_err = NULL; >>> >>> if (!clock_get(cs->clock)) { >>> +#ifdef CONFIG_USER_ONLY >>> /* >>> * Initialize the frequency to 200MHz in case >>> * the clock remains unconnected. >>> */ >>> clock_set_hz(cs->clock, 200000000); >>> +#else >>> + if (!qtest_enabled()) { >>> + error_setg(errp, "CPU clock must be connected to a clock source"); >>> + return; >>> + } >>> +#endif >>> } >>> mips_cpu_clk_update(cs); >>> >> >