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[2.142.241.104]) by smtp.gmail.com with ESMTPSA id o10sm14655694wri.15.2021.11.10.03.11.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Nov 2021 03:11:24 -0800 (PST) Subject: Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> <20211110070452.48539-11-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: <30642177-1f52-08fb-c3ed-77492fdc7cc8@linaro.org> Date: Wed, 10 Nov 2021 12:11:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211110070452.48539-11-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.678, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/10/21 8:04 AM, LIU Zhiwei wrote: > The mask comes from the pointer masking extension, or the max value > corresponding to XLEN bits. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 4 ++++ > target/riscv/cpu_helper.c | 40 ++++++++++++++++++++++++++++++++++++ > target/riscv/csr.c | 19 +++++++++++++++++ > target/riscv/machine.c | 10 +++++++++ > target/riscv/vector_helper.c | 23 +++++++++++++-------- > 6 files changed, 88 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0d2d175fa2..886388f066 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -378,6 +378,7 @@ static void riscv_cpu_reset(DeviceState *dev) > #ifndef CONFIG_USER_ONLY > env->misa_mxl = env->misa_mxl_max; > env->priv = PRV_M; > + riscv_cpu_update_mask(env); > env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); > if (env->misa_mxl > MXL_RV32) { > /* > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 11590a510e..73d7aa9ad7 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -252,6 +252,8 @@ struct CPURISCVState { > target_ulong upmmask; > target_ulong upmbase; > #endif > + target_ulong mask; > + target_ulong base; I think the name here isn't great. Without the context of the preceeding elements, the question becomes: mask of what? Better might be cur_pmmask, cur_pmbase. Broader than that, you're doing too many things in this patch. The subject is "adjust vector address with mask", but you're also creating new fields and updating them at priv changes, etc. Too much. > +void riscv_cpu_update_mask(CPURISCVState *env) ... update_pmmask? > +} > + > + > + Watch the extra spaces. > @@ -1571,6 +1572,9 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno, > uint64_t mstatus; > > env->mpmmask = val; > + if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { > + env->mask = val; > + } This needs to use the function; there are pieces missing here, notably the zero-extend for RV32. I don't see any updates to the exception entry and exception return paths. You'll want to update the translator to use these new fields instead of using the [msu]pmmask / [msu]pmbase fields directly. (Which means that we will have fewer tcg variables, and need not copy the "current" into DisasContext.) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 60006b1b1b..0b297f6bc8 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -123,6 +123,11 @@ static inline uint32_t vext_maxsz(uint32_t desc) > return simd_maxsz(desc) << vext_lmul(desc); > } > > +static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) > +{ > + return (addr & env->mask) | env->base; > +} The code here in vector_helper.c looks fine as a patch by itself, under the subject that you have given. r~