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[83.57.172.113]) by smtp.gmail.com with ESMTPSA id r5sm37145399wrt.43.2020.01.18.01.09.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 18 Jan 2020 01:09:54 -0800 (PST) Subject: Re: [PATCH v3 10/17] hw/arm/allwinner-h3: add Boot ROM support To: Niek Linnenbank References: <20200108200020.4745-1-nieklinnenbank@gmail.com> <20200108200020.4745-11-nieklinnenbank@gmail.com> <9c878f16-b18c-cc1a-9e82-40dbdd31b823@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <316c94b7-fea2-f44e-6d31-10fb41b09be3@redhat.com> Date: Sat, 18 Jan 2020 10:09:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: 1cgWZQMcN2Caz53cyAa-9A-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/15/20 12:10 AM, Niek Linnenbank wrote: > On Tue, Jan 14, 2020 at 12:28 AM Philippe Mathieu-Daud=C3=A9=20 > > wrote: >=20 > On 1/8/20 9:00 PM, Niek Linnenbank wrote: > > A real Allwinner H3 SoC contains a Boot ROM which is the > > first code that runs right after the SoC is powered on. > > The Boot ROM is responsible for loading user code (e.g. a bootload= er) > > from any of the supported external devices and writing the downloa= ded > > code to internal SRAM. After loading the SoC begins executing the > code > > written to SRAM. This commits adds emulation of the Boot ROM firmw= are > > setup functionality by loading user code from SD card. > > > > Signed-off-by: Niek Linnenbank > > > --- > >=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h | 23 +++++++++++++++++++= ++++ > >=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0| 28 ++++++++++++++++++++++++++++ > >=C2=A0 =C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 3 +++ > >=C2=A0 =C2=A03 files changed, 54 insertions(+) > > > > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > > index 5d74cca28e..4b66227ac4 100644 > > --- a/include/hw/arm/allwinner-h3.h > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -50,6 +50,7 @@ > >=C2=A0 =C2=A0#include "hw/sd/allwinner-sdhost.h" > >=C2=A0 =C2=A0#include "hw/net/allwinner-sun8i-emac.h" > >=C2=A0 =C2=A0#include "target/arm/cpu.h" > > +#include "sysemu/block-backend.h" > > > >=C2=A0 =C2=A0/** > >=C2=A0 =C2=A0 * Allwinner H3 device list > > @@ -130,4 +131,26 @@ typedef struct AwH3State { > >=C2=A0 =C2=A0 =C2=A0 =C2=A0MemoryRegion sram_c; > >=C2=A0 =C2=A0} AwH3State; > > > > +/** > > + * Emulate Boot ROM firmware setup functionality. > > + * > > + * A real Allwinner H3 SoC contains a Boot ROM > > + * which is the first code that runs right after > > + * the SoC is powered on. The Boot ROM is responsible > > + * for loading user code (e.g. a bootloader) from any > > + * of the supported external devices and writing the > > + * downloaded code to internal SRAM. After loading the SoC > > + * begins executing the code written to SRAM. > > + * > > + * This function emulates the Boot ROM by copying 32 KiB > > + * of data from the given block device and writes it to > > + * the start of the first internal SRAM memory. > > + * > > + * @s: Allwinner H3 state object pointer > > + * @blk: Block backend device object pointer > > + * @errp: Error object pointer for raising errors > > + */ > > +void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk, > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Error **errp); > > + > >=C2=A0 =C2=A0#endif /* HW_ARM_ALLWINNER_H3_H */ > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > index e692432b4e..e7b768ad5b 100644 > > --- a/hw/arm/allwinner-h3.c > > +++ b/hw/arm/allwinner-h3.c > > @@ -27,6 +27,7 @@ > >=C2=A0 =C2=A0#include "hw/char/serial.h" > >=C2=A0 =C2=A0#include "hw/misc/unimp.h" > >=C2=A0 =C2=A0#include "hw/usb/hcd-ehci.h" > > +#include "hw/loader.h" > >=C2=A0 =C2=A0#include "sysemu/sysemu.h" > >=C2=A0 =C2=A0#include "hw/arm/allwinner-h3.h" > > > > @@ -168,6 +169,33 @@ enum { > >=C2=A0 =C2=A0 =C2=A0 =C2=A0AW_H3_GIC_NUM_SPI=C2=A0 =C2=A0 =C2=A0 = =C2=A0=3D 128 > >=C2=A0 =C2=A0}; > > > > +void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk, > Error **errp) > > +{ > > +=C2=A0 =C2=A0 uint8_t *buffer; > > +=C2=A0 =C2=A0 int64_t rom_size =3D 32 * KiB; >=20 > Why restrict to 32K? The A1 SRAM is 64K. >=20 >=20 > The reason is that the actual Boot ROM on the H3 also uses 32K: > https://linux-sunxi.org/BROM >=20 > See the 'U-Boot SPL Limitations' table at the end of the page. >=20 > You can see the comment in the table there regarding the 32 KiB: > =C2=A0 "Sizes larger than 32 KiB are rejected by the BROM. Exactly 32 Ki= B is=20 > fine, as verified by writing a special pattern at the end of the SPL and= =20 > checking it in the SRAM." > Probably it would not harm to increase it to the full size of the SRAM,= =20 > but I tried to model > the behavior as close to the real hardware as possible. OK, then please document this difference in the commit description -=20 such "While the A1 SRAM is 64K, we limit to 32K because ..." - and add a=20 reference to https://linux-sunxi.org/BROM#U-Boot_SPL_limitations