* [Qemu-devel] [PATCH v4 00/16] data-driven device registers
@ 2016-02-09 22:14 Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree Alistair Francis
` (16 more replies)
0 siblings, 17 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
This patch series is based on Peter C's original register API. His
original cover letter is below.
I have added a new function memory_region_add_subregion_no_print() which
stops memory regions from being printed by 'info mtree'. This is used to
avoid evey register being printed when running 'info mtree'.
NOTE: That info qom-tree will still print all of these registers.
Future work: Allow support for memory attributes.
V4:
- Rebase and fix build issue
- Simplify the register write logic
- Other small fixes suggested by Alex Bennee
V3:
- Small changes reported by Fred
V2:
- Rebase
- Fix up IOU SLCR connections
- Add the memory_region_add_subregion_no_print() function and use it
for the registers
Changes since RFC:
- Connect the ZynqMP IOU SLCR device
- Rebase
Original cover letter From Peter:
Hi All. This is a new scheme I've come up with handling device registers in a
data driven way. My motivation for this is to factor out a lot of the access
checking that seems to be replicated in every device. See P1 commit message for
further discussion.
P1 is the main patch, adds the register definition functionality
P2-3,6 add helpers that glue the register API to the Memory API
P4 Defines a set of macros that minimise register and field definitions
P5 is QOMfication
P7 is a trivial
P10-13 Work up to GPIO support
P8,9,14 add new devices (the Xilinx Zynq devcfg & ZynqMP SLCR) that use this
scheme.
P15: Connect the ZynqMP SLCR device
This Zynq devcfg device was particularly finnicky with per-bit restrictions.
I'm also looking for a higher-than-usual modelling fidelity
on the register space, with semantics defined for random reserved bits
in-between otherwise consistent fields.
Here's an example of the qemu_log output for the devcfg device. This is produced
by now generic sharable code:
/machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508
/machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010
/machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value ffffffff
/machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f
And an example of a rogue guest banging on a bad bit:
/machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not be \
written to 1
A future feature I am interested in is implementing TCG optimisation of
side-effectless registers. The register API allows clear definition of
what registers have txn side effects and which ones don't. You could even
go a step further and translate such side-effectless accesses based on the
data pointer for the register.
Alistair Francis (3):
memory: Allow subregions to not be printed by info mtree
register: Add Register API
xlnx-zynqmp: Connect the ZynqMP IOU SLCR
Peter Crosthwaite (13):
register: Add Memory API glue
register: Add support for decoding information
register: Define REG and FIELD macros
register: QOMify
register: Add block initialise helper
bitops: Add ONES macro
dma: Add Xilinx Zynq devcfg device model
xilinx_zynq: add devcfg to machine model
qdev: Define qdev_get_gpio_out
qdev: Add qdev_pass_all_gpios API
irq: Add opaque setter routine
register: Add GPIO API
misc: Introduce ZynqMP IOU SLCR
default-configs/arm-softmmu.mak | 1 +
hw/arm/xilinx_zynq.c | 8 +
hw/arm/xlnx-zynqmp.c | 13 ++
hw/core/Makefile.objs | 1 +
hw/core/irq.c | 5 +
hw/core/qdev.c | 21 ++
hw/core/register.c | 348 +++++++++++++++++++++++++++++
hw/dma/Makefile.objs | 1 +
hw/dma/xlnx-zynq-devcfg.c | 393 +++++++++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/xlnx-zynqmp-iou-slcr.c | 113 ++++++++++
include/exec/memory.h | 17 ++
include/hw/arm/xlnx-zynqmp.h | 2 +
include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
include/hw/irq.h | 2 +
include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++
include/hw/qdev-core.h | 3 +
include/hw/register.h | 260 ++++++++++++++++++++++
include/qemu/bitops.h | 2 +
memory.c | 10 +-
20 files changed, 1309 insertions(+), 1 deletion(-)
create mode 100644 hw/core/register.c
create mode 100644 hw/dma/xlnx-zynq-devcfg.c
create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c
create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h
create mode 100644 include/hw/register.h
--
2.5.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-26 16:51 ` Alex Bennée
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 02/16] register: Add Register API Alistair Francis
` (15 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
Add a function called memory_region_add_subregion_no_print() that
creates memory subregions that won't be printed when running
the 'info mtree' command.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
include/exec/memory.h | 17 +++++++++++++++++
memory.c | 10 +++++++++-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index c92734a..25353df 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -186,6 +186,7 @@ struct MemoryRegion {
bool skip_dump;
bool enabled;
bool warning_printed; /* For reservations */
+ bool do_not_print;
uint8_t vga_logging_count;
MemoryRegion *alias;
hwaddr alias_offset;
@@ -954,6 +955,22 @@ void memory_region_del_eventfd(MemoryRegion *mr,
void memory_region_add_subregion(MemoryRegion *mr,
hwaddr offset,
MemoryRegion *subregion);
+
+/**
+ * memory_region_add_subregion_no_print: Add a subregion to a container.
+ *
+ * The same functionality as memory_region_add_subregion except that any
+ * memory regions added by this function are not printed by 'info mtree'.
+ *
+ * @mr: the region to contain the new subregion; must be a container
+ * initialized with memory_region_init().
+ * @offset: the offset relative to @mr where @subregion is added.
+ * @subregion: the subregion to be added.
+ */
+void memory_region_add_subregion_no_print(MemoryRegion *mr,
+ hwaddr offset,
+ MemoryRegion *subregion);
+
/**
* memory_region_add_subregion_overlap: Add a subregion to a container
* with overlap.
diff --git a/memory.c b/memory.c
index 09041ed..228a8a7 100644
--- a/memory.c
+++ b/memory.c
@@ -1829,6 +1829,14 @@ void memory_region_add_subregion(MemoryRegion *mr,
memory_region_add_subregion_common(mr, offset, subregion);
}
+void memory_region_add_subregion_no_print(MemoryRegion *mr,
+ hwaddr offset,
+ MemoryRegion *subregion)
+{
+ memory_region_add_subregion(mr, offset, subregion);
+ subregion->do_not_print = true;
+}
+
void memory_region_add_subregion_overlap(MemoryRegion *mr,
hwaddr offset,
MemoryRegion *subregion,
@@ -2219,7 +2227,7 @@ static void mtree_print_mr(fprintf_function mon_printf, void *f,
const MemoryRegion *submr;
unsigned int i;
- if (!mr) {
+ if (!mr || mr->do_not_print) {
return;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 02/16] register: Add Register API
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-26 17:13 ` Alex Bennée
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 03/16] register: Add Memory API glue Alistair Francis
` (14 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
This API provides some encapsulation of registers and factors our some
common functionality to common code. Bits of device state (usually MMIO
registers), often have all sorts of access restrictions and semantics
associated with them. This API allow you to define what those
restrictions are on a bit-by-bit basis.
Helper functions are then used to access the register which observe the
semantics defined by the RegisterAccessInfo struct.
Some features:
Bits can be marked as read_only (ro field)
Bits can be marked as write-1-clear (w1c field)
Bits can be marked as reserved (rsvd field)
Reset values can be defined (reset)
Bits can throw guest errors when written certain values (ge0, ge1)
Bits can throw unimp errors when written certain values (ui0, ui1)
Bits can be marked clear on read (cor)
Pre and post action callbacks can be added to read and write ops
Verbose debugging info can be enabled/disabled
Useful for defining device register spaces in a data driven way. Cuts
down on a lot of the verbosity and repetition in the switch-case blocks
in the standard foo_mmio_read/write functions.
Also useful for automated generation of device models from hardware
design sources.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V4:
- Rebase
- Remove the guest error masking
- Simplify the unimplemented masking
- Use the reserved value in the write calculations
- Remove read_lite and write_lite
- General fixes to asserts and log printing
V3:
- Address some comments from Fred
hw/core/Makefile.objs | 1 +
hw/core/register.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/register.h | 111 ++++++++++++++++++++++++++++++++++++
3 files changed, 264 insertions(+)
create mode 100644 hw/core/register.c
create mode 100644 include/hw/register.h
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index abb3560..bf95db5 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -14,4 +14,5 @@ common-obj-$(CONFIG_SOFTMMU) += machine.o
common-obj-$(CONFIG_SOFTMMU) += null-machine.o
common-obj-$(CONFIG_SOFTMMU) += loader.o
common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
+common-obj-$(CONFIG_SOFTMMU) += register.o
common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o
diff --git a/hw/core/register.c b/hw/core/register.c
new file mode 100644
index 0000000..7e47df5
--- /dev/null
+++ b/hw/core/register.c
@@ -0,0 +1,152 @@
+/*
+ * Register Definition API
+ *
+ * Copyright (c) 2013 Xilinx Inc.
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "hw/register.h"
+#include "hw/qdev.h"
+#include "qemu/log.h"
+
+static inline void register_write_log(int mask, RegisterInfo *reg, int dir,
+ uint64_t val, const char *msg,
+ const char *reason)
+{
+ qemu_log_mask(mask, "%s:%s bits %#" PRIx64 " %s write of %d%s%s\n",
+ reg->prefix, reg->access->name, val, msg, dir,
+ reason ? ": " : "", reason ? reason : "");
+}
+
+static inline void register_write_val(RegisterInfo *reg, uint64_t val)
+{
+ g_assert(reg->data);
+
+ switch (reg->data_size) {
+ case 1:
+ *(uint8_t *)reg->data = val;
+ break;
+ case 2:
+ *(uint16_t *)reg->data = val;
+ break;
+ case 4:
+ *(uint32_t *)reg->data = val;
+ break;
+ case 8:
+ *(uint64_t *)reg->data = val;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static inline uint64_t register_read_val(RegisterInfo *reg)
+{
+ switch (reg->data_size) {
+ case 1:
+ return *(uint8_t *)reg->data;
+ case 2:
+ return *(uint16_t *)reg->data;
+ case 4:
+ return *(uint32_t *)reg->data;
+ case 8:
+ return *(uint64_t *)reg->data;
+ default:
+ g_assert_not_reached();
+ }
+ return 0; /* unreachable */
+}
+
+void register_write(RegisterInfo *reg, uint64_t val, uint64_t we)
+{
+ uint64_t old_val, new_val, test, no_w_mask;
+ const RegisterAccessInfo *ac;
+
+ assert(reg);
+
+ ac = reg->access;
+
+ if (!ac || !ac->name) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
+ "(written value: %#" PRIx64 ")\n", reg->prefix, val);
+ return;
+ }
+
+ old_val = reg->data ? register_read_val(reg) : ac->reset;
+
+ test = (old_val ^ val) & ac->rsvd;
+ if (test) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit"
+ "fields: %#" PRIx64 ")\n", reg->prefix, test);
+ }
+
+ test = val & ac->unimp;
+ if (test) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s:%s writing %#" PRIx64 " to unimplemented bits:" \
+ " %#" PRIx64 "",
+ reg->prefix, reg->access->name, val, ac->unimp);
+ }
+
+
+ no_w_mask = ac->ro | ac->w1c | ac->rsvd | ~we;
+ new_val = (val & ~no_w_mask) | (old_val & no_w_mask);
+ new_val &= ~(val & ac->w1c);
+
+ if (ac->pre_write) {
+ new_val = ac->pre_write(reg, new_val);
+ }
+
+ if (reg->debug) {
+ qemu_log("%s:%s: write of value %#" PRIx64 "\n", reg->prefix, ac->name,
+ new_val);
+ }
+
+ register_write_val(reg, new_val);
+
+ if (ac->post_write) {
+ ac->post_write(reg, new_val);
+ }
+}
+
+uint64_t register_read(RegisterInfo *reg)
+{
+ uint64_t ret;
+ const RegisterAccessInfo *ac;
+
+ assert(reg);
+
+ ac = reg->access;
+ if (!ac || !ac->name) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read from undefined device state\n",
+ reg->prefix);
+ return 0;
+ }
+
+ ret = reg->data ? register_read_val(reg) : ac->reset;
+
+ register_write_val(reg, ret & ~ac->cor);
+
+ if (ac->post_read) {
+ ret = ac->post_read(reg, ret);
+ }
+
+ if (reg->debug) {
+ qemu_log("%s:%s: read of value %#" PRIx64 "\n", reg->prefix,
+ ac->name, ret);
+ }
+
+ return ret;
+}
+
+void register_reset(RegisterInfo *reg)
+{
+ g_assert(reg);
+ g_assert(reg->data);
+ g_assert(reg->access);
+
+ register_write_val(reg, reg->access->reset);
+}
diff --git a/include/hw/register.h b/include/hw/register.h
new file mode 100644
index 0000000..444239c
--- /dev/null
+++ b/include/hw/register.h
@@ -0,0 +1,111 @@
+/*
+ * Register Definition API
+ *
+ * Copyright (c) 2013 Xilinx Inc.
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef REGISTER_H
+#define REGISTER_H
+
+#include "exec/memory.h"
+
+typedef struct RegisterInfo RegisterInfo;
+typedef struct RegisterAccessInfo RegisterAccessInfo;
+
+/**
+ * Access description for a register that is part of guest accessible device
+ * state.
+ *
+ * @name: String name of the register
+ * @ro: whether or not the bit is read-only
+ * @w1c: bits with the common write 1 to clear semantic.
+ * @reset: reset value.
+ * @cor: Bits that are clear on read
+ * @rsvd: Bits that are reserved and should not be changed
+ *
+ * @ui1: Bits that when written 1 indicate use of an unimplemented feature
+ * @ui0: Bits that when written 0 indicate use of an unimplemented feature
+ *
+ * @pre_write: Pre write callback. Passed the value that's to be written,
+ * immediately before the actual write. The returned value is what is written,
+ * giving the handler a chance to modify the written value.
+ * @post_write: Post write callback. Passed the written value. Most write side
+ * effects should be implemented here.
+ *
+ * @post_read: Post read callback. Passes the value that is about to be returned
+ * for a read. The return value from this function is what is ultimately read,
+ * allowing this function to modify the value before return to the client.
+ */
+
+struct RegisterAccessInfo {
+ const char *name;
+ uint64_t ro;
+ uint64_t w1c;
+ uint64_t reset;
+ uint64_t cor;
+ uint64_t rsvd;
+ uint64_t unimp;
+
+ uint64_t (*pre_write)(RegisterInfo *reg, uint64_t val);
+ void (*post_write)(RegisterInfo *reg, uint64_t val);
+
+ uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
+};
+
+/**
+ * A register that is part of guest accessible state
+ * @data: pointer to the register data. Will be cast
+ * to the relevant uint type depending on data_size.
+ * @data_size: Size of the register in bytes. Must be
+ * 1, 2, 4 or 8
+ *
+ * @access: Access description of this register
+ *
+ * @debug: Whether or not verbose debug is enabled
+ * @prefix: String prefix for log and debug messages
+ *
+ * @opaque: Opaque data for the register
+ */
+
+struct RegisterInfo {
+ /* <public> */
+ void *data;
+ int data_size;
+
+ const RegisterAccessInfo *access;
+
+ bool debug;
+ const char *prefix;
+
+ void *opaque;
+};
+
+/**
+ * write a value to a register, subject to its restrictions
+ * @reg: register to write to
+ * @val: value to write
+ * @we: write enable mask
+ */
+
+void register_write(RegisterInfo *reg, uint64_t val, uint64_t we);
+
+/**
+ * read a value from a register, subject to its restrictions
+ * @reg: register to read from
+ * returns: value read
+ */
+
+uint64_t register_read(RegisterInfo *reg);
+
+/**
+ * reset a register
+ * @reg: register to reset
+ */
+
+void register_reset(RegisterInfo *reg);
+
+#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 03/16] register: Add Memory API glue
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 02/16] register: Add Register API Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-26 17:25 ` Alex Bennée
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 04/16] register: Add support for decoding information Alistair Francis
` (13 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add memory io handlers that glue the register API to the memory API.
Just translation functions at this stage. Although it does allow for
devices to be created without all-in-one mmio r/w handlers.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/core/register.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/register.h | 31 +++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index 7e47df5..9cd50c8 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -150,3 +150,51 @@ void register_reset(RegisterInfo *reg)
register_write_val(reg, reg->access->reset);
}
+
+static inline void register_write_memory(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size, bool be)
+{
+ RegisterInfo *reg = opaque;
+ uint64_t we = ~0;
+ int shift = 0;
+
+ if (reg->data_size != size) {
+ we = (size == 8) ? ~0ull : (1ull << size * 8) - 1;
+ shift = 8 * (be ? reg->data_size - size - addr : addr);
+ }
+
+ assert(size + addr <= reg->data_size);
+ register_write(reg, value << shift, we << shift);
+}
+
+void register_write_memory_be(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ register_write_memory(opaque, addr, value, size, true);
+}
+
+
+void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ register_write_memory(opaque, addr, value, size, false);
+}
+
+static inline uint64_t register_read_memory(void *opaque, hwaddr addr,
+ unsigned size, bool be)
+{
+ RegisterInfo *reg = opaque;
+ int shift = 8 * (be ? reg->data_size - size - addr : addr);
+
+ return register_read(reg) >> shift;
+}
+
+uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size)
+{
+ return register_read_memory(opaque, addr, size, true);
+}
+
+uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size)
+{
+ return register_read_memory(opaque, addr, size, false);
+}
diff --git a/include/hw/register.h b/include/hw/register.h
index 444239c..9aa9cfc 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -69,9 +69,14 @@ struct RegisterAccessInfo {
* @prefix: String prefix for log and debug messages
*
* @opaque: Opaque data for the register
+ *
+ * @mem: optional Memory region for the register
*/
struct RegisterInfo {
+ /* <private> */
+ MemoryRegion mem;
+
/* <public> */
void *data;
int data_size;
@@ -108,4 +113,30 @@ uint64_t register_read(RegisterInfo *reg);
void register_reset(RegisterInfo *reg);
+/**
+ * Memory API MMIO write handler that will write to a Register API register.
+ * _be for big endian variant and _le for little endian.
+ * @opaque: RegisterInfo to write to
+ * @addr: Address to write
+ * @value: Value to write
+ * @size: Number of bytes to write
+ */
+
+void register_write_memory_be(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size);
+void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size);
+
+/**
+ * Memory API MMIO read handler that will read from a Register API register.
+ * _be for big endian variant and _le for little endian.
+ * @opaque: RegisterInfo to read from
+ * @addr: Address to read
+ * @size: Number of bytes to read
+ * returns: Value read from register
+ */
+
+uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size);
+uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size);
+
#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 04/16] register: Add support for decoding information
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (2 preceding siblings ...)
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 03/16] register: Add Memory API glue Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 05/16] register: Define REG and FIELD macros Alistair Francis
` (12 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Allow defining of optional address decoding information in register
definitions. This is useful for clients that want to associate
registers with specific addresses.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V3:
- Remove unused flags option
include/hw/register.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/hw/register.h b/include/hw/register.h
index 9aa9cfc..29edb5b 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -41,6 +41,11 @@ typedef struct RegisterAccessInfo RegisterAccessInfo;
* allowing this function to modify the value before return to the client.
*/
+#define REG_DECODE_READ (1 << 0)
+#define REG_DECODE_WRITE (1 << 1)
+#define REG_DECODE_EXECUTE (1 << 2)
+#define REG_DECODE_RW (REG_DECODE_READ | REG_DECODE_WRITE)
+
struct RegisterAccessInfo {
const char *name;
uint64_t ro;
@@ -54,6 +59,10 @@ struct RegisterAccessInfo {
void (*post_write)(RegisterInfo *reg, uint64_t val);
uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
+
+ struct {
+ hwaddr addr;
+ } decode;
};
/**
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 05/16] register: Define REG and FIELD macros
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (3 preceding siblings ...)
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 04/16] register: Add support for decoding information Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 06/16] register: QOMify Alistair Francis
` (11 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Define some macros that can be used for defining registers and fields.
The REG32 macro will define A_FOO, for the byte address of a register
as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and
FOO_BAR_LENGTH constants for field BAR in register FOO.
Finally, there are some shorthand helpers for extracting/depositing
fields from registers based on these naming schemes.
Usage can greatly reduce the verbosity of device code.
The deposit and extract macros (eg F_EX32, AF_DP32 etc.) can be used
to generate extract and deposits without any repetition of the name
stems.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[ EI Changes:
* Add Deposit macros
]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
E.g. Currently you have to define something like:
\#define R_FOOREG (0x84/4)
\#define R_FOOREG_BARFIELD_SHIFT 10
\#define R_FOOREG_BARFIELD_LENGTH 5
uint32_t foobar_val = extract32(s->regs[R_FOOREG],
R_FOOREG_BARFIELD_SHIFT,
R_FOOREG_BARFIELD_LENGTH);
Which has:
2 macro definitions per field
3 register names ("FOOREG") per extract
2 field names ("BARFIELD") per extract
With these macros this becomes:
REG32(FOOREG, 0x84)
FIELD(FOOREG, BARFIELD, 10, 5)
uint32_t foobar_val = AF_EX32(s->regs, FOOREG, BARFIELD)
Which has:
1 macro definition per field
1 register name per extract
1 field name per extract
If you are not using arrays for the register data you can just use the
non-array "F_" variants and still save 2 name stems:
uint32_t foobar_val = F_EX32(s->fooreg, FOOREG, BARFIELD)
Deposit is similar for depositing values. Deposit has compile-time
overflow checking for literals.
For example:
REG32(XYZ1, 0x84)
FIELD(XYZ1, TRC, 0, 4)
/* Correctly set XYZ1.TRC = 5. */
AF_DP32(s->regs, XYZ1, TRC, 5);
/* Incorrectly set XYZ1.TRC = 16. */
AF_DP32(s->regs, XYZ1, TRC, 16);
The latter assignment results in:
warning: large integer implicitly truncated to unsigned type [-Woverflow]
include/hw/register.h | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/include/hw/register.h b/include/hw/register.h
index 29edb5b..bd03f50 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -148,4 +148,42 @@ void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size);
uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size);
+/* Define constants for a 32 bit register */
+#define REG32(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 4 };
+
+/* Define SHIFT, LEGTH and MASK constants for a field within a register */
+#define FIELD(reg, field, shift, length) \
+ enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
+ enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
+ enum { R_ ## reg ## _ ## field ## _MASK = (((1ULL << (length)) - 1) \
+ << (shift)) };
+
+/* Extract a field from a register */
+
+#define F_EX32(storage, reg, field) \
+ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
+
+/* Extract a field from an array of registers */
+
+#define AF_EX32(regs, reg, field) \
+ F_EX32((regs)[R_ ## reg], reg, field)
+
+/* Deposit a register field. */
+
+#define F_DP32(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint32_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
+
+/* Deposit a field to array of registers. */
+
+#define AF_DP32(regs, reg, field, val) \
+ (regs)[R_ ## reg] = F_DP32((regs)[R_ ## reg], reg, field, val);
#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 06/16] register: QOMify
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (4 preceding siblings ...)
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 05/16] register: Define REG and FIELD macros Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper Alistair Francis
` (10 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
QOMify registers as a child of TYPE_DEVICE. This allows registers to
define GPIOs.
Define an init helper that will do QOM initialisation as well as setup
the r/w fast paths.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/core/register.c | 23 +++++++++++++++++++++++
include/hw/register.h | 14 ++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index 9cd50c8..d766517 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -151,6 +151,17 @@ void register_reset(RegisterInfo *reg)
register_write_val(reg, reg->access->reset);
}
+void register_init(RegisterInfo *reg)
+{
+ assert(reg);
+
+ if (!reg->data || !reg->access) {
+ return;
+ }
+
+ object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER);
+}
+
static inline void register_write_memory(void *opaque, hwaddr addr,
uint64_t value, unsigned size, bool be)
{
@@ -198,3 +209,15 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size)
{
return register_read_memory(opaque, addr, size, false);
}
+
+static const TypeInfo register_info = {
+ .name = TYPE_REGISTER,
+ .parent = TYPE_DEVICE,
+};
+
+static void register_register_types(void)
+{
+ type_register_static(®ister_info);
+}
+
+type_init(register_register_types)
diff --git a/include/hw/register.h b/include/hw/register.h
index bd03f50..d3469c6 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -11,6 +11,7 @@
#ifndef REGISTER_H
#define REGISTER_H
+#include "hw/qdev-core.h"
#include "exec/memory.h"
typedef struct RegisterInfo RegisterInfo;
@@ -84,6 +85,8 @@ struct RegisterAccessInfo {
struct RegisterInfo {
/* <private> */
+ DeviceState parent_obj;
+
MemoryRegion mem;
/* <public> */
@@ -98,6 +101,9 @@ struct RegisterInfo {
void *opaque;
};
+#define TYPE_REGISTER "qemu,register"
+#define REGISTER(obj) OBJECT_CHECK(RegisterInfo, (obj), TYPE_REGISTER)
+
/**
* write a value to a register, subject to its restrictions
* @reg: register to write to
@@ -123,6 +129,14 @@ uint64_t register_read(RegisterInfo *reg);
void register_reset(RegisterInfo *reg);
/**
+ * Initialize a register. GPIO's are setup as IOs to the specified device.
+ * Fast paths for eligible registers are enabled.
+ * @reg: Register to initialize
+ */
+
+void register_init(RegisterInfo *reg);
+
+/**
* Memory API MMIO write handler that will write to a Register API register.
* _be for big endian variant and _le for little endian.
* @opaque: RegisterInfo to write to
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (5 preceding siblings ...)
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 06/16] register: QOMify Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-29 11:28 ` Alex Bennée
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro Alistair Francis
` (9 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add a helper that will scan a static RegisterAccessInfo Array
and populate a container MemoryRegion with registers as defined.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V3:
- Fix typo
V2:
- Use memory_region_add_subregion_no_print()
hw/core/register.c | 29 +++++++++++++++++++++++++++++
include/hw/register.h | 20 ++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index d766517..ac866f6 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -210,6 +210,35 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size)
return register_read_memory(opaque, addr, size, false);
}
+void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
+ int num, RegisterInfo *ri, uint32_t *data,
+ MemoryRegion *container, const MemoryRegionOps *ops,
+ bool debug_enabled)
+{
+ const char *debug_prefix = object_get_typename(OBJECT(owner));
+ int i;
+
+ for (i = 0; i < num; i++) {
+ int index = rae[i].decode.addr / 4;
+ RegisterInfo *r = &ri[index];
+
+ *r = (RegisterInfo) {
+ .data = &data[index],
+ .data_size = sizeof(uint32_t),
+ .access = &rae[i],
+ .debug = debug_enabled,
+ .prefix = debug_prefix,
+ .opaque = owner,
+ };
+ register_init(r);
+
+ memory_region_init_io(&r->mem, OBJECT(owner), ops, r, r->access->name,
+ sizeof(uint32_t));
+ memory_region_add_subregion_no_print(container,
+ r->access->decode.addr, &r->mem);
+ }
+}
+
static const TypeInfo register_info = {
.name = TYPE_REGISTER,
.parent = TYPE_DEVICE,
diff --git a/include/hw/register.h b/include/hw/register.h
index d3469c6..6ac005c 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -162,6 +162,26 @@ void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size);
uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size);
+/**
+ * Init a block of consecutive registers into a container MemoryRegion. A
+ * number of constant register definitions are parsed to create a corresponding
+ * array of RegisterInfo's.
+ *
+ * @owner: device owning the registers
+ * @rae: Register definitions to init
+ * @num: number of registers to init (length of @rae)
+ * @ri: Register array to init
+ * @data: Array to use for register data
+ * @container: Memory region to contain new registers
+ * @ops: Memory region ops to access registers.
+ * @debug enabled: turn on/off verbose debug information
+ */
+
+void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
+ int num, RegisterInfo *ri, uint32_t *data,
+ MemoryRegion *container, const MemoryRegionOps *ops,
+ bool debug_enabled);
+
/* Define constants for a 32 bit register */
#define REG32(reg, addr) \
enum { A_ ## reg = (addr) }; \
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (6 preceding siblings ...)
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-29 11:51 ` Alex Bennée
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model Alistair Francis
` (8 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Little macro that just gives you N ones (justified to LSB).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
include/qemu/bitops.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 8164225..27bf98d 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -430,4 +430,6 @@ static inline uint64_t deposit64(uint64_t value, int start, int length,
return (value & ~mask) | ((fieldval << start) & mask);
}
+#define ONES(num) ((num) == 64 ? ~0ull : (1ull << (num)) - 1)
+
#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (7 preceding siblings ...)
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro Alistair Francis
@ 2016-02-09 22:14 ` Alistair Francis
2016-02-29 12:20 ` Alex Bennée
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 11/16] qdev: Define qdev_get_gpio_out Alistair Francis
` (7 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:14 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Minimal device model for devcfg module of Zynq. DMA capabilities and
interrupt generation supported.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/dma/Makefile.objs | 1 +
hw/dma/xlnx-zynq-devcfg.c | 397 ++++++++++++++++++++++++++++++++++++++
include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
4 files changed, 461 insertions(+)
create mode 100644 hw/dma/xlnx-zynq-devcfg.c
create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a9f82a1..d524584 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -66,6 +66,7 @@ CONFIG_PXA2XX=y
CONFIG_BITBANG_I2C=y
CONFIG_FRAMEBUFFER=y
CONFIG_XILINX_SPIPS=y
+CONFIG_ZYNQ_DEVCFG=y
CONFIG_ARM11SCU=y
CONFIG_A9SCU=y
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 0e65ed0..eaf0a81 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -5,6 +5,7 @@ common-obj-$(CONFIG_PL330) += pl330.o
common-obj-$(CONFIG_I82374) += i82374.o
common-obj-$(CONFIG_I8257) += i8257.o
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
+common-obj-$(CONFIG_ZYNQ_DEVCFG) += xlnx-zynq-devcfg.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
new file mode 100644
index 0000000..0420123
--- /dev/null
+++ b/hw/dma/xlnx-zynq-devcfg.c
@@ -0,0 +1,397 @@
+/*
+ * QEMU model of the Xilinx Zynq Devcfg Interface
+ *
+ * (C) 2011 PetaLogix Pty Ltd
+ * (C) 2014 Xilinx Inc.
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/dma/xlnx-zynq-devcfg.h"
+#include "qemu/bitops.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/dma.h"
+
+#define FREQ_HZ 900000000
+
+#define BTT_MAX 0x400
+
+#ifndef XLNX_ZYNQ_DEVCFG_ERR_DEBUG
+#define XLNX_ZYNQ_DEVCFG_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT(...) do { \
+ if (XLNX_ZYNQ_DEVCFG_ERR_DEBUG) { \
+ qemu_log("%s: ", __func__); \
+ qemu_log(__VA_ARGS__); \
+ } \
+} while (0);
+
+REG32(CTRL, 0x00)
+ FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */
+ FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
+ FIELD(CTRL, PCAP_MODE, 26, 1)
+ FIELD(CTRL, MULTIBOOT_EN, 24, 1)
+ FIELD(CTRL, USER_MODE, 15, 1)
+ FIELD(CTRL, PCFG_AES_FUSE, 12, 1)
+ FIELD(CTRL, PCFG_AES_EN, 9, 3)
+ FIELD(CTRL, SEU_EN, 8, 1)
+ FIELD(CTRL, SEC_EN, 7, 1)
+ FIELD(CTRL, SPNIDEN, 6, 1)
+ FIELD(CTRL, SPIDEN, 5, 1)
+ FIELD(CTRL, NIDEN, 4, 1)
+ FIELD(CTRL, DBGEN, 3, 1)
+ FIELD(CTRL, DAP_EN, 0, 3)
+
+REG32(LOCK, 0x04)
+ #define AES_FUSE_LOCK 4
+ #define AES_EN_LOCK 3
+ #define SEU_LOCK 2
+ #define SEC_LOCK 1
+ #define DBG_LOCK 0
+
+/* mapping bits in R_LOCK to what they lock in R_CTRL */
+static const uint32_t lock_ctrl_map[] = {
+ [AES_FUSE_LOCK] = R_CTRL_PCFG_AES_FUSE_MASK,
+ [AES_EN_LOCK] = R_CTRL_PCFG_AES_EN_MASK,
+ [SEU_LOCK] = R_CTRL_SEU_EN_MASK,
+ [SEC_LOCK] = R_CTRL_SEC_EN_MASK,
+ [DBG_LOCK] = R_CTRL_SPNIDEN_MASK | R_CTRL_SPIDEN_MASK |
+ R_CTRL_NIDEN_MASK | R_CTRL_DBGEN_MASK |
+ R_CTRL_DAP_EN_MASK,
+};
+
+REG32(CFG, 0x08)
+ FIELD(CFG, RFIFO_TH, 10, 2)
+ FIELD(CFG, WFIFO_TH, 8, 2)
+ FIELD(CFG, RCLK_EDGE, 7, 1)
+ FIELD(CFG, WCLK_EDGE, 6, 1)
+ FIELD(CFG, DISABLE_SRC_INC, 5, 1)
+ FIELD(CFG, DISABLE_DST_INC, 4, 1)
+#define R_CFG_RO 0xFFFFF000
+#define R_CFG_RESET 0x50B
+
+REG32(INT_STS, 0x0C)
+ FIELD(INT_STS, PSS_GTS_USR_B, 31, 1)
+ FIELD(INT_STS, PSS_FST_CFG_B, 30, 1)
+ FIELD(INT_STS, PSS_CFG_RESET_B, 27, 1)
+ FIELD(INT_STS, RX_FIFO_OV, 18, 1)
+ FIELD(INT_STS, WR_FIFO_LVL, 17, 1)
+ FIELD(INT_STS, RD_FIFO_LVL, 16, 1)
+ FIELD(INT_STS, DMA_CMD_ERR, 15, 1)
+ FIELD(INT_STS, DMA_Q_OV, 14, 1)
+ FIELD(INT_STS, DMA_DONE, 13, 1)
+ FIELD(INT_STS, DMA_P_DONE, 12, 1)
+ FIELD(INT_STS, P2D_LEN_ERR, 11, 1)
+ FIELD(INT_STS, PCFG_DONE, 2, 1)
+ #define R_INT_STS_RSVD ((0x7 << 24) | (0x1 << 19) | (0xF < 7))
+
+REG32(INT_MASK, 0x10)
+
+REG32(STATUS, 0x14)
+ FIELD(STATUS, DMA_CMD_Q_F, 31, 1)
+ FIELD(STATUS, DMA_CMD_Q_E, 30, 1)
+ FIELD(STATUS, DMA_DONE_CNT, 28, 2)
+ FIELD(STATUS, RX_FIFO_LVL, 20, 5)
+ FIELD(STATUS, TX_FIFO_LVL, 12, 7)
+ FIELD(STATUS, PSS_GTS_USR_B, 11, 1)
+ FIELD(STATUS, PSS_FST_CFG_B, 10, 1)
+ FIELD(STATUS, PSS_CFG_RESET_B, 5, 1)
+
+REG32(DMA_SRC_ADDR, 0x18)
+REG32(DMA_DST_ADDR, 0x1C)
+REG32(DMA_SRC_LEN, 0x20)
+REG32(DMA_DST_LEN, 0x24)
+REG32(ROM_SHADOW, 0x28)
+REG32(SW_ID, 0x30)
+REG32(UNLOCK, 0x34)
+
+#define R_UNLOCK_MAGIC 0x757BDF0D
+
+REG32(MCTRL, 0x80)
+ FIELD(MCTRL, PS_VERSION, 28, 4)
+ FIELD(MCTRL, PCFG_POR_B, 8, 1)
+ FIELD(MCTRL, INT_PCAP_LPBK, 4, 1)
+ FIELD(MCTRL, QEMU, 3, 1)
+
+static void xlnx_zynq_devcfg_update_ixr(XlnxZynqDevcfg *s)
+{
+ qemu_set_irq(s->irq, ~s->regs[R_INT_MASK] & s->regs[R_INT_STS]);
+}
+
+static void xlnx_zynq_devcfg_reset(DeviceState *dev)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(dev);
+ int i;
+
+ for (i = 0; i < XLNX_ZYNQ_DEVCFG_R_MAX; ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static void xlnx_zynq_devcfg_dma_go(XlnxZynqDevcfg *s)
+{
+ for (;;) {
+ uint8_t buf[BTT_MAX];
+ XlnxZynqDevcfgDMACmd *dmah = s->dma_cmd_fifo;
+ uint32_t btt = BTT_MAX;
+ bool loopback = s->regs[R_MCTRL] & R_MCTRL_INT_PCAP_LPBK_MASK;
+
+ btt = MIN(btt, dmah->src_len);
+ if (loopback) {
+ btt = MIN(btt, dmah->dest_len);
+ }
+ DB_PRINT("reading %x bytes from %x\n", btt, dmah->src_addr);
+ dma_memory_read(&address_space_memory, dmah->src_addr, buf, btt);
+ dmah->src_len -= btt;
+ dmah->src_addr += btt;
+ if (loopback) {
+ DB_PRINT("writing %x bytes from %x\n", btt, dmah->dest_addr);
+ dma_memory_write(&address_space_memory, dmah->dest_addr, buf, btt);
+ dmah->dest_len -= btt;
+ dmah->dest_addr += btt;
+ }
+ if (!dmah->src_len && !dmah->dest_len) {
+ DB_PRINT("dma operation finished\n");
+ s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
+ R_INT_STS_DMA_P_DONE_MASK;
+ s->dma_cmd_fifo_num--;
+ memmove(s->dma_cmd_fifo, &s->dma_cmd_fifo[1],
+ sizeof(*s->dma_cmd_fifo) * XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN
+ - 1);
+ }
+ xlnx_zynq_devcfg_update_ixr(s);
+ if (!s->dma_cmd_fifo_num) { /* All done */
+ return;
+ }
+ }
+}
+
+static void r_ixr_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+
+ xlnx_zynq_devcfg_update_ixr(s);
+}
+
+static uint64_t r_ctrl_pre_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(lock_ctrl_map); ++i) {
+ if (s->regs[R_LOCK] & 1 << i) {
+ val &= ~lock_ctrl_map[i];
+ val |= lock_ctrl_map[i] & s->regs[R_CTRL];
+ }
+ }
+ return val;
+}
+
+static void r_ctrl_post_write(RegisterInfo *reg, uint64_t val)
+{
+ uint32_t aes_en = F_EX32(val, CTRL, PCFG_AES_EN);
+
+ if (aes_en != 0 && aes_en != 7) {
+ qemu_log_mask(LOG_UNIMP, "%s: warning, aes-en bits inconsistent,"
+ "unimplemented security reset should happen!\n",
+ reg->prefix);
+ }
+}
+
+static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+
+ if (val == R_UNLOCK_MAGIC) {
+ DB_PRINT("successful unlock\n");
+ /* BootROM will have already done the actual unlock so no need to do
+ * anything in successful subsequent unlock
+ */
+ } else { /* bad unlock attempt */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: failed unlock\n", reg->prefix);
+ s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK;
+ s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK;
+ /* core becomes inaccessible */
+ memory_region_set_enabled(&s->iomem, false);
+ }
+}
+
+static uint64_t r_lock_pre_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+
+ /* once bits are locked they stay locked */
+ return s->regs[R_LOCK] | val;
+}
+
+static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+
+ s->dma_cmd_fifo[s->dma_cmd_fifo_num] = (XlnxZynqDevcfgDMACmd) {
+ .src_addr = s->regs[R_DMA_SRC_ADDR] & ~0x3UL,
+ .dest_addr = s->regs[R_DMA_DST_ADDR] & ~0x3UL,
+ .src_len = s->regs[R_DMA_SRC_LEN] << 2,
+ .dest_len = s->regs[R_DMA_DST_LEN] << 2,
+ };
+ s->dma_cmd_fifo_num++;
+ DB_PRINT("dma transfer started; %d total transfers pending\n",
+ s->dma_cmd_fifo_num);
+ xlnx_zynq_devcfg_dma_go(s);
+}
+
+static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
+ { .name = "CTRL", .decode.addr = A_CTRL,
+ .reset = R_CTRL_PCAP_PR_MASK | R_CTRL_PCAP_MODE_MASK | 0x3 << 13,
+ .rsvd = 0x1 << 28 | 0x3ff << 13 | 0x3 << 13,
+ .pre_write = r_ctrl_pre_write,
+ .post_write = r_ctrl_post_write,
+ },
+ { .name = "LOCK", .decode.addr = A_LOCK,
+ .rsvd = ~ONES(5),
+ .pre_write = r_lock_pre_write,
+ },
+ { .name = "CFG", .decode.addr = A_CFG,
+ .reset = 1 << R_CFG_RFIFO_TH_SHIFT | 1 << R_CFG_WFIFO_TH_SHIFT | 0x8,
+ .rsvd = 0xfffff00f,
+ },
+ { .name = "INT_STS", .decode.addr = A_INT_STS,
+ .w1c = ~R_INT_STS_RSVD,
+ .reset = R_INT_STS_PSS_GTS_USR_B_MASK |
+ R_INT_STS_PSS_CFG_RESET_B_MASK |
+ R_INT_STS_WR_FIFO_LVL_MASK,
+ .rsvd = R_INT_STS_RSVD,
+ .post_write = r_ixr_post_write,
+ },
+ { .name = "INT_MASK", .decode.addr = A_INT_MASK,
+ .reset = ~0,
+ .rsvd = R_INT_STS_RSVD,
+ .post_write = r_ixr_post_write,
+ },
+ { .name = "STATUS", .decode.addr = A_STATUS,
+ .reset = R_STATUS_DMA_CMD_Q_E_MASK |
+ R_STATUS_PSS_GTS_USR_B_MASK |
+ R_STATUS_PSS_CFG_RESET_B_MASK,
+ .ro = ~0,
+ },
+ { .name = "DMA_SRC_ADDR", .decode.addr = A_DMA_SRC_ADDR, },
+ { .name = "DMA_DST_ADDR", .decode.addr = A_DMA_DST_ADDR, },
+ { .name = "DMA_SRC_LEN", .decode.addr = A_DMA_SRC_LEN,
+ .ro = ~ONES(27) },
+ { .name = "DMA_DST_LEN", .decode.addr = A_DMA_DST_LEN,
+ .ro = ~ONES(27),
+ .post_write = r_dma_dst_len_post_write,
+ },
+ { .name = "ROM_SHADOW", .decode.addr = A_ROM_SHADOW,
+ .rsvd = ~0ull,
+ },
+ { .name = "SW_ID", .decode.addr = A_SW_ID, },
+ { .name = "UNLOCK", .decode.addr = A_UNLOCK,
+ .post_write = r_unlock_post_write,
+ },
+ { .name = "MCTRL", .decode.addr = R_MCTRL * 4,
+ /* Silicon 3.0 for version field, the mysterious reserved bit 23
+ * and QEMU platform identifier.
+ */
+ .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU_MASK,
+ .ro = ~R_MCTRL_INT_PCAP_LPBK_MASK,
+ .rsvd = 0x00f00303,
+ },
+};
+
+static const MemoryRegionOps xlnx_zynq_devcfg_reg_ops = {
+ .read = register_read_memory_le,
+ .write = register_write_memory_le,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static const VMStateDescription vmstate_xlnx_zynq_devcfg_dma_cmd = {
+ .name = "xlnx_zynq_devcfg_dma_cmd",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(src_addr, XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT32(dest_addr, XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT32(src_len, XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT32(dest_len, XlnxZynqDevcfgDMACmd),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_xlnx_zynq_devcfg = {
+ .name = "xlnx_zynq_devcfg",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(dma_cmd_fifo, XlnxZynqDevcfg,
+ XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN, 0,
+ vmstate_xlnx_zynq_devcfg_dma_cmd,
+ XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT8(dma_cmd_fifo_num, XlnxZynqDevcfg),
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG_R_MAX),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void xlnx_zynq_devcfg_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(obj);
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ memory_region_init(&s->iomem, obj, "devcfg", XLNX_ZYNQ_DEVCFG_R_MAX * 4);
+ register_init_block32(DEVICE(obj), xlnx_zynq_devcfg_regs_info,
+ ARRAY_SIZE(xlnx_zynq_devcfg_regs_info),
+ s->regs_info, s->regs, &s->iomem,
+ &xlnx_zynq_devcfg_reg_ops,
+ XLNX_ZYNQ_DEVCFG_ERR_DEBUG);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void xlnx_zynq_devcfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = xlnx_zynq_devcfg_reset;
+ dc->vmsd = &vmstate_xlnx_zynq_devcfg;
+}
+
+static const TypeInfo xlnx_zynq_devcfg_info = {
+ .name = TYPE_XLNX_ZYNQ_DEVCFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqDevcfg),
+ .instance_init = xlnx_zynq_devcfg_init,
+ .class_init = xlnx_zynq_devcfg_class_init,
+};
+
+static void xlnx_zynq_devcfg_register_types(void)
+{
+ type_register_static(&xlnx_zynq_devcfg_info);
+}
+
+type_init(xlnx_zynq_devcfg_register_types)
diff --git a/include/hw/dma/xlnx-zynq-devcfg.h b/include/hw/dma/xlnx-zynq-devcfg.h
new file mode 100644
index 0000000..d40e5c8
--- /dev/null
+++ b/include/hw/dma/xlnx-zynq-devcfg.h
@@ -0,0 +1,62 @@
+/*
+ * QEMU model of the Xilinx Devcfg Interface
+ *
+ * (C) 2011 PetaLogix Pty Ltd
+ * (C) 2014 Xilinx Inc.
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef XLNX_ZYNQ_DEVCFG_H
+
+#include "hw/register.h"
+#include "hw/sysbus.h"
+
+#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
+
+#define XLNX_ZYNQ_DEVCFG(obj) \
+ OBJECT_CHECK(XlnxZynqDevcfg, (obj), TYPE_XLNX_ZYNQ_DEVCFG)
+
+#define XLNX_ZYNQ_DEVCFG_R_MAX 0x118
+
+#define XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN 10
+
+typedef struct XlnxZynqDevcfgDMACmd {
+ uint32_t src_addr;
+ uint32_t dest_addr;
+ uint32_t src_len;
+ uint32_t dest_len;
+} XlnxZynqDevcfgDMACmd;
+
+typedef struct XlnxZynqDevcfg {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ XlnxZynqDevcfgDMACmd dma_cmd_fifo[XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN];
+ uint8_t dma_cmd_fifo_num;
+
+ uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
+ RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
+} XlnxZynqDevcfg;
+
+#define XLNX_ZYNQ_DEVCFG_H
+#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 11/16] qdev: Define qdev_get_gpio_out
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (8 preceding siblings ...)
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model Alistair Francis
@ 2016-02-09 22:15 ` Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 12/16] qdev: Add qdev_pass_all_gpios API Alistair Francis
` (6 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:15 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
An API similar to the existing qdev_get_gpio_in() except gets outputs.
Useful for:
1: Implementing lightweight devices that don't want to keep pointers
to their own GPIOs. They can get their GPIO pointers at runtime from
QOM using this API.
2: testing or debugging code which may wish to override the
hardware generated value of of a GPIO with a user specified value
(E.G. interrupt injection).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/core/qdev.c | 12 ++++++++++++
include/hw/qdev-core.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index db41aa1..e3015d2 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -489,6 +489,18 @@ qemu_irq qdev_get_gpio_in(DeviceState *dev, int n)
return qdev_get_gpio_in_named(dev, NULL, n);
}
+qemu_irq qdev_get_gpio_out_named(DeviceState *dev, const char *name, int n)
+{
+ char *propname = g_strdup_printf("%s[%d]",
+ name ? name : "unnamed-gpio-out", n);
+ return (qemu_irq)object_property_get_link(OBJECT(dev), propname, NULL);
+}
+
+qemu_irq qdev_get_gpio_out(DeviceState *dev, int n)
+{
+ return qdev_get_gpio_out_named(dev, NULL, n);
+}
+
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
qemu_irq pin)
{
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index abcdee8..0a09b8a 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -287,6 +287,8 @@ bool qdev_machine_modified(void);
qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n);
+qemu_irq qdev_get_gpio_out(DeviceState *dev, int n);
+qemu_irq qdev_get_gpio_out_named(DeviceState *dev, const char *name, int n);
void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 12/16] qdev: Add qdev_pass_all_gpios API
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (9 preceding siblings ...)
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 11/16] qdev: Define qdev_get_gpio_out Alistair Francis
@ 2016-02-09 22:15 ` Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 13/16] irq: Add opaque setter routine Alistair Francis
` (5 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:15 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
For passing all GPIOs of all names from a contained device to a
container.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/core/qdev.c | 9 +++++++++
include/hw/qdev-core.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index e3015d2..371fba0 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -589,6 +589,15 @@ void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
QLIST_INSERT_HEAD(&container->gpios, ngl, node);
}
+void qdev_pass_all_gpios(DeviceState *dev, DeviceState *container)
+{
+ NamedGPIOList *ngl;
+
+ QLIST_FOREACH(ngl, &dev->gpios, node) {
+ qdev_pass_gpios(dev, container, ngl->name);
+ }
+}
+
BusState *qdev_get_child_bus(DeviceState *dev, const char *name)
{
BusState *bus;
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 0a09b8a..753673c 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -312,6 +312,7 @@ void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
const char *name);
+void qdev_pass_all_gpios(DeviceState *dev, DeviceState *container);
BusState *qdev_get_parent_bus(DeviceState *dev);
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 13/16] irq: Add opaque setter routine
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (10 preceding siblings ...)
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 12/16] qdev: Add qdev_pass_all_gpios API Alistair Francis
@ 2016-02-09 22:15 ` Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API Alistair Francis
` (4 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:15 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add a routine to set or override the opaque data of an IRQ.
Qdev currently always initialises IRQ opaque as the device itself.
This allows you to override to a custom opaque in the case where
there is extra or different data needed.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/core/irq.c | 5 +++++
include/hw/irq.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6..9d125fb 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -77,6 +77,11 @@ qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n)
return irq;
}
+void qemu_irq_set_opaque(qemu_irq irq, void *opaque)
+{
+ irq->opaque = opaque;
+}
+
void qemu_free_irqs(qemu_irq *s, int n)
{
int i;
diff --git a/include/hw/irq.h b/include/hw/irq.h
index 4c4c2ea..edad0fc 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -44,6 +44,8 @@ qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n);
qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler,
void *opaque, int n);
+void qemu_irq_set_opaque(qemu_irq irq, void *opaque);
+
void qemu_free_irqs(qemu_irq *s, int n);
void qemu_free_irq(qemu_irq irq);
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (11 preceding siblings ...)
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 13/16] irq: Add opaque setter routine Alistair Francis
@ 2016-02-09 22:15 ` Alistair Francis
2016-02-29 12:22 ` Alex Bennée
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 15/16] misc: Introduce ZynqMP IOU SLCR Alistair Francis
` (3 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:15 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add GPIO functionality to the register API. This allows association
and automatic connection of GPIOs to bits in registers. GPIO inputs
will attach to handlers that automatically set read-only bits in
registers. GPIO outputs will be updated to reflect their field value
when their respective registers are written (or reset). Supports
active low GPIOs.
This is particularly effective for implementing system level
controllers, where heterogenous collections of control signals are
placed is a SoC specific peripheral then propagated all over the
system.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[ EI Changes:
* register: Add a polarity field to GPIO connections
Makes it possible to directly connect active low signals
to generic interrupt pins.
]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/core/register.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/register.h | 37 ++++++++++++++++++++
2 files changed, 133 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index ac866f6..1dc7ccc 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -106,6 +106,7 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we)
}
register_write_val(reg, new_val);
+ register_refresh_gpios(reg, old_val);
if (ac->post_write) {
ac->post_write(reg, new_val);
@@ -147,19 +148,113 @@ void register_reset(RegisterInfo *reg)
g_assert(reg);
g_assert(reg->data);
g_assert(reg->access);
+ uint64_t old_val;
+
+ old_val = register_read_val(reg);
register_write_val(reg, reg->access->reset);
+ register_refresh_gpios(reg, old_val);
+}
+
+void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value)
+{
+ const RegisterAccessInfo *ac;
+ const RegisterGPIOMapping *gpio;
+
+ ac = reg->access;
+ for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
+ int i;
+
+ if (gpio->input) {
+ continue;
+ }
+
+ for (i = 0; i < gpio->num; ++i) {
+ uint64_t gpio_value, gpio_value_old;
+
+ qemu_irq gpo = qdev_get_gpio_out_named(DEVICE(reg), gpio->name, i);
+ gpio_value_old = extract64(old_value,
+ gpio->bit_pos + i * gpio->width,
+ gpio->width) ^ gpio->polarity;
+ gpio_value = extract64(register_read_val(reg),
+ gpio->bit_pos + i * gpio->width,
+ gpio->width) ^ gpio->polarity;
+ if (!(gpio_value_old ^ gpio_value)) {
+ continue;
+ }
+ if (reg->debug && gpo) {
+ qemu_log("refreshing gpio out %s to %" PRIx64 "\n",
+ gpio->name, gpio_value);
+ }
+ qemu_set_irq(gpo, gpio_value);
+ }
+ }
+}
+
+typedef struct DeviceNamedGPIOHandlerOpaque {
+ DeviceState *dev;
+ const char *name;
+} DeviceNamedGPIOHandlerOpaque;
+
+static void register_gpio_handler(void *opaque, int n, int level)
+{
+ DeviceNamedGPIOHandlerOpaque *gho = opaque;
+ RegisterInfo *reg = REGISTER(gho->dev);
+
+ const RegisterAccessInfo *ac;
+ const RegisterGPIOMapping *gpio;
+
+ ac = reg->access;
+ for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
+ if (gpio->input && !strcmp(gho->name, gpio->name)) {
+ register_write_val(reg, deposit64(register_read_val(reg),
+ gpio->bit_pos + n * gpio->width,
+ gpio->width,
+ level ^ gpio->polarity));
+ return;
+ }
+ }
+
+ abort();
}
void register_init(RegisterInfo *reg)
{
assert(reg);
+ const RegisterAccessInfo *ac;
+ const RegisterGPIOMapping *gpio;
if (!reg->data || !reg->access) {
return;
}
object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER);
+
+ ac = reg->access;
+ for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
+ if (!gpio->num) {
+ ((RegisterGPIOMapping *)gpio)->num = 1;
+ }
+ if (!gpio->width) {
+ ((RegisterGPIOMapping *)gpio)->width = 1;
+ }
+ if (gpio->input) {
+ DeviceNamedGPIOHandlerOpaque gho = {
+ .name = gpio->name,
+ .dev = DEVICE(reg),
+ };
+ qemu_irq irq;
+
+ qdev_init_gpio_in_named(DEVICE(reg), register_gpio_handler,
+ gpio->name, gpio->num);
+ irq = qdev_get_gpio_in_named(DEVICE(reg), gpio->name, gpio->num);
+ qemu_irq_set_opaque(irq, g_memdup(&gho, sizeof(gho)));
+ } else {
+ qemu_irq *gpos = g_new0(qemu_irq, gpio->num);
+
+ qdev_init_gpio_out_named(DEVICE(reg), gpos, gpio->name, gpio->num);
+ }
+ }
}
static inline void register_write_memory(void *opaque, hwaddr addr,
@@ -231,6 +326,7 @@ void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
.opaque = owner,
};
register_init(r);
+ qdev_pass_all_gpios(DEVICE(r), owner);
memory_region_init_io(&r->mem, OBJECT(owner), ops, r, r->access->name,
sizeof(uint32_t));
diff --git a/include/hw/register.h b/include/hw/register.h
index 6ac005c..4d284a9 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -13,11 +13,35 @@
#include "hw/qdev-core.h"
#include "exec/memory.h"
+#include "hw/irq.h"
typedef struct RegisterInfo RegisterInfo;
typedef struct RegisterAccessInfo RegisterAccessInfo;
/**
+ * A register access error message
+ * @mask: Bits in the register the error applies to
+ * @reason: Reason why this access is an error
+ */
+
+typedef struct RegisterAccessError {
+ uint64_t mask;
+ const char *reason;
+} RegisterAccessError;
+
+#define REG_GPIO_POL_HIGH 0
+#define REG_GPIO_POL_LOW 1
+
+typedef struct RegisterGPIOMapping {
+ const char *name;
+ uint8_t bit_pos;
+ bool input;
+ bool polarity;
+ uint8_t num;
+ uint8_t width;
+} RegisterGPIOMapping;
+
+/**
* Access description for a register that is part of guest accessible device
* state.
*
@@ -61,6 +85,8 @@ struct RegisterAccessInfo {
uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
+ const RegisterGPIOMapping *gpios;
+
struct {
hwaddr addr;
} decode;
@@ -137,6 +163,17 @@ void register_reset(RegisterInfo *reg);
void register_init(RegisterInfo *reg);
/**
+ * Refresh GPIO outputs based on diff between old value register current value.
+ * GPIOs are refreshed for fields where the old value differs to the current
+ * value.
+ *
+ * @reg: Register to refresh GPIO outs
+ * @old_value: previous value of register
+ */
+
+void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value);
+
+/**
* Memory API MMIO write handler that will write to a Register API register.
* _be for big endian variant and _le for little endian.
* @opaque: RegisterInfo to write to
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 15/16] misc: Introduce ZynqMP IOU SLCR
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (12 preceding siblings ...)
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API Alistair Francis
@ 2016-02-09 22:15 ` Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the " Alistair Francis
` (2 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:15 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
IOU = I/O Unit
SLCR = System Level Control Registers
This IP is a misc collections of control registers that switch various
properties of system IPs. Currently the only thing implemented is the
SD_SLOTTYPE control (implemented as a GPIO output).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/xlnx-zynqmp-iou-slcr.c | 113 +++++++++++++++++++++++++++++++++
include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++++++++++++
3 files changed, 161 insertions(+)
create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c
create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ea6cd3c..eef3e40 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -41,6 +41,7 @@ obj-$(CONFIG_RASPI) += bcm2835_property.o
obj-$(CONFIG_SLAVIO) += slavio_misc.o
obj-$(CONFIG_ZYNQ) += zynq_slcr.o
obj-$(CONFIG_ZYNQ) += zynq-xadc.o
+obj-$(CONFIG_ZYNQ) += xlnx-zynqmp-iou-slcr.o
obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
diff --git a/hw/misc/xlnx-zynqmp-iou-slcr.c b/hw/misc/xlnx-zynqmp-iou-slcr.c
new file mode 100644
index 0000000..35b989c
--- /dev/null
+++ b/hw/misc/xlnx-zynqmp-iou-slcr.c
@@ -0,0 +1,113 @@
+/*
+ * Xilinx ZynqMP IOU System Level Control Registers (SLCR)
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/misc/xlnx-zynqmp-iou-slcr.h"
+
+#ifndef XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG
+#define XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG 0
+#endif
+
+REG32(SD_SLOTTYPE, 0x310)
+ #define R_SD_SLOTTYPE_RSVD 0xffff7ffe
+
+static const RegisterAccessInfo xlnx_zynqmp_iou_slcr_regs_info[] = {
+ { .name = "SD Slot TYPE", .decode.addr = A_SD_SLOTTYPE,
+ .rsvd = R_SD_SLOTTYPE_RSVD,
+ .gpios = (RegisterGPIOMapping []) {
+ { .name = "SD0_SLOTTYPE", .bit_pos = 0 },
+ { .name = "SD1_SLOTTYPE", .bit_pos = 15 },
+ {},
+ }
+ }
+ /* FIXME: Complete device model */
+};
+
+static void xlnx_zynqmp_iou_slcr_reset(DeviceState *dev)
+{
+ XlnxZynqMPIOUSLCR *s = XLNX_ZYNQMP_IOU_SLCR(dev);
+ int i;
+
+ for (i = 0; i < XLNX_ZYNQ_MP_IOU_SLCR_R_MAX; ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static const MemoryRegionOps xlnx_zynqmp_iou_slcr_ops = {
+ .read = register_read_memory_le,
+ .write = register_write_memory_le,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static void xlnx_zynqmp_iou_slcr_init(Object *obj)
+{
+ XlnxZynqMPIOUSLCR *s = XLNX_ZYNQMP_IOU_SLCR(obj);
+
+ memory_region_init(&s->iomem, obj, "MMIO", XLNX_ZYNQ_MP_IOU_SLCR_R_MAX * 4);
+ register_init_block32(DEVICE(obj), xlnx_zynqmp_iou_slcr_regs_info,
+ ARRAY_SIZE(xlnx_zynqmp_iou_slcr_regs_info),
+ s->regs_info, s->regs, &s->iomem,
+ &xlnx_zynqmp_iou_slcr_ops,
+ XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static const VMStateDescription vmstate_xlnx_zynqmp_iou_slcr = {
+ .name = "xlnx_zynqmp_iou_slcr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIOUSLCR,
+ XLNX_ZYNQ_MP_IOU_SLCR_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void xlnx_zynqmp_iou_slcr_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = xlnx_zynqmp_iou_slcr_reset;
+ dc->vmsd = &vmstate_xlnx_zynqmp_iou_slcr;
+}
+
+static const TypeInfo xlnx_zynqmp_iou_slcr_info = {
+ .name = TYPE_XLNX_ZYNQMP_IOU_SLCR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqMPIOUSLCR),
+ .class_init = xlnx_zynqmp_iou_slcr_class_init,
+ .instance_init = xlnx_zynqmp_iou_slcr_init,
+};
+
+static void xlnx_zynqmp_iou_slcr_register_types(void)
+{
+ type_register_static(&xlnx_zynqmp_iou_slcr_info);
+}
+
+type_init(xlnx_zynqmp_iou_slcr_register_types)
diff --git a/include/hw/misc/xlnx-zynqmp-iou-slcr.h b/include/hw/misc/xlnx-zynqmp-iou-slcr.h
new file mode 100644
index 0000000..1a3f7e9
--- /dev/null
+++ b/include/hw/misc/xlnx-zynqmp-iou-slcr.h
@@ -0,0 +1,47 @@
+/*
+ * Xilinx ZynqMP IOU system level control registers (SLCR)
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+
+#define TYPE_XLNX_ZYNQMP_IOU_SLCR "xlnx_zynqmp-iou-slcr"
+
+#define XLNX_ZYNQMP_IOU_SLCR(obj) \
+ OBJECT_CHECK(XlnxZynqMPIOUSLCR, (obj), TYPE_XLNX_ZYNQMP_IOU_SLCR)
+
+#define XLNX_ZYNQ_MP_IOU_SLCR_R_MAX (0x314/4)
+
+typedef struct XlnxZynqMPIOUSLCR XlnxZynqMPIOUSLCR;
+
+struct XlnxZynqMPIOUSLCR {
+ /*< private >*/
+ SysBusDevice busdev;
+
+ /*< public >*/
+ MemoryRegion iomem;
+
+ uint32_t regs[XLNX_ZYNQ_MP_IOU_SLCR_R_MAX];
+ RegisterInfo regs_info[XLNX_ZYNQ_MP_IOU_SLCR_R_MAX];
+};
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the ZynqMP IOU SLCR
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (13 preceding siblings ...)
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 15/16] misc: Introduce ZynqMP IOU SLCR Alistair Francis
@ 2016-02-09 22:15 ` Alistair Francis
2016-02-26 16:15 ` [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alex Bennée
2016-02-29 12:26 ` Alex Bennée
16 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-02-09 22:15 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: edgar.iglesias, alistair.francis, crosthwaitepeter,
edgar.iglesias, alex.bennee, afaerber, fred.konrad
Connect the I/O Unit System Level Control Registers device
to the ZynqMP model. Unfortunatly the GPIO links can not be
connected yet as the SD device is not yet attached to the
ZynqMP machine.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
- Fix up device connection
hw/arm/xlnx-zynqmp.c | 13 +++++++++++++
include/hw/arm/xlnx-zynqmp.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 1508d08..6d1b797 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -33,6 +33,8 @@
#define SATA_ADDR 0xFD0C0000
#define SATA_NUM_PORTS 2
+#define IOU_SLCR_ADDR 0xFF180000
+
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};
@@ -132,6 +134,10 @@ static void xlnx_zynqmp_init(Object *obj)
TYPE_XILINX_SPIPS);
qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
}
+
+ object_initialize(&s->iou_slcr, sizeof(s->iou_slcr),
+ TYPE_XLNX_ZYNQMP_IOU_SLCR);
+ qdev_set_parent_bus(DEVICE(&s->iou_slcr), sysbus_get_default());
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -355,6 +361,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
&error_abort);
g_free(bus_name);
}
+
+ object_property_set_bool(OBJECT(&s->iou_slcr), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->iou_slcr), 0, IOU_SLCR_ADDR);
}
static Property xlnx_zynqmp_props[] = {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 2332596..8fff0ae 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,7 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
+#include "hw/misc/xlnx-zynqmp-iou-slcr.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/sd/sdhci.h"
@@ -81,6 +82,7 @@ typedef struct XlnxZynqMPState {
SysbusAHCIState sata;
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
+ XlnxZynqMPIOUSLCR iou_slcr;
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/16] data-driven device registers
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (14 preceding siblings ...)
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the " Alistair Francis
@ 2016-02-26 16:15 ` Alex Bennée
2016-02-29 12:26 ` Alex Bennée
16 siblings, 0 replies; 35+ messages in thread
From: Alex Bennée @ 2016-02-26 16:15 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> This patch series is based on Peter C's original register API. His
> original cover letter is below.
In the next revision you'll need to add the osdep includes that
currently break this when applied to origin/master.
See:
https://travis-ci.org/stsquad/qemu/builds/112038657
>
> I have added a new function memory_region_add_subregion_no_print() which
> stops memory regions from being printed by 'info mtree'. This is used to
> avoid evey register being printed when running 'info mtree'.
>
> NOTE: That info qom-tree will still print all of these registers.
>
> Future work: Allow support for memory attributes.
>
> V4:
> - Rebase and fix build issue
> - Simplify the register write logic
> - Other small fixes suggested by Alex Bennee
> V3:
> - Small changes reported by Fred
> V2:
> - Rebase
> - Fix up IOU SLCR connections
> - Add the memory_region_add_subregion_no_print() function and use it
> for the registers
> Changes since RFC:
> - Connect the ZynqMP IOU SLCR device
> - Rebase
>
> Original cover letter From Peter:
> Hi All. This is a new scheme I've come up with handling device registers in a
> data driven way. My motivation for this is to factor out a lot of the access
> checking that seems to be replicated in every device. See P1 commit message for
> further discussion.
>
> P1 is the main patch, adds the register definition functionality
> P2-3,6 add helpers that glue the register API to the Memory API
> P4 Defines a set of macros that minimise register and field definitions
> P5 is QOMfication
> P7 is a trivial
> P10-13 Work up to GPIO support
> P8,9,14 add new devices (the Xilinx Zynq devcfg & ZynqMP SLCR) that use this
> scheme.
> P15: Connect the ZynqMP SLCR device
>
> This Zynq devcfg device was particularly finnicky with per-bit restrictions.
> I'm also looking for a higher-than-usual modelling fidelity
> on the register space, with semantics defined for random reserved bits
> in-between otherwise consistent fields.
>
> Here's an example of the qemu_log output for the devcfg device. This is produced
> by now generic sharable code:
>
> /machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508
> /machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010
> /machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value ffffffff
> /machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f
>
> And an example of a rogue guest banging on a bad bit:
>
> /machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not be \
> written to 1
>
> A future feature I am interested in is implementing TCG optimisation of
> side-effectless registers. The register API allows clear definition of
> what registers have txn side effects and which ones don't. You could even
> go a step further and translate such side-effectless accesses based on the
> data pointer for the register.
>
>
> Alistair Francis (3):
> memory: Allow subregions to not be printed by info mtree
> register: Add Register API
> xlnx-zynqmp: Connect the ZynqMP IOU SLCR
>
> Peter Crosthwaite (13):
> register: Add Memory API glue
> register: Add support for decoding information
> register: Define REG and FIELD macros
> register: QOMify
> register: Add block initialise helper
> bitops: Add ONES macro
> dma: Add Xilinx Zynq devcfg device model
> xilinx_zynq: add devcfg to machine model
> qdev: Define qdev_get_gpio_out
> qdev: Add qdev_pass_all_gpios API
> irq: Add opaque setter routine
> register: Add GPIO API
> misc: Introduce ZynqMP IOU SLCR
>
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/xilinx_zynq.c | 8 +
> hw/arm/xlnx-zynqmp.c | 13 ++
> hw/core/Makefile.objs | 1 +
> hw/core/irq.c | 5 +
> hw/core/qdev.c | 21 ++
> hw/core/register.c | 348 +++++++++++++++++++++++++++++
> hw/dma/Makefile.objs | 1 +
> hw/dma/xlnx-zynq-devcfg.c | 393 +++++++++++++++++++++++++++++++++
> hw/misc/Makefile.objs | 1 +
> hw/misc/xlnx-zynqmp-iou-slcr.c | 113 ++++++++++
> include/exec/memory.h | 17 ++
> include/hw/arm/xlnx-zynqmp.h | 2 +
> include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
> include/hw/irq.h | 2 +
> include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++
> include/hw/qdev-core.h | 3 +
> include/hw/register.h | 260 ++++++++++++++++++++++
> include/qemu/bitops.h | 2 +
> memory.c | 10 +-
> 20 files changed, 1309 insertions(+), 1 deletion(-)
> create mode 100644 hw/core/register.c
> create mode 100644 hw/dma/xlnx-zynq-devcfg.c
> create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c
> create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
> create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h
> create mode 100644 include/hw/register.h
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree Alistair Francis
@ 2016-02-26 16:51 ` Alex Bennée
2016-02-26 16:54 ` Peter Maydell
0 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-26 16:51 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> Add a function called memory_region_add_subregion_no_print() that
> creates memory subregions that won't be printed when running
> the 'info mtree' command.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
>
> include/exec/memory.h | 17 +++++++++++++++++
> memory.c | 10 +++++++++-
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/include/exec/memory.h b/include/exec/memory.h
> index c92734a..25353df 100644
> --- a/include/exec/memory.h
> +++ b/include/exec/memory.h
> @@ -186,6 +186,7 @@ struct MemoryRegion {
> bool skip_dump;
> bool enabled;
> bool warning_printed; /* For reservations */
> + bool do_not_print;
> uint8_t vga_logging_count;
> MemoryRegion *alias;
> hwaddr alias_offset;
> @@ -954,6 +955,22 @@ void memory_region_del_eventfd(MemoryRegion *mr,
> void memory_region_add_subregion(MemoryRegion *mr,
> hwaddr offset,
> MemoryRegion *subregion);
> +
> +/**
> + * memory_region_add_subregion_no_print: Add a subregion to a container.
> + *
> + * The same functionality as memory_region_add_subregion except that any
> + * memory regions added by this function are not printed by 'info mtree'.
> + *
> + * @mr: the region to contain the new subregion; must be a container
> + * initialized with memory_region_init().
> + * @offset: the offset relative to @mr where @subregion is added.
> + * @subregion: the subregion to be added.
> + */
> +void memory_region_add_subregion_no_print(MemoryRegion *mr,
> + hwaddr offset,
> + MemoryRegion *subregion);
> +
I think this needlessly complicates the memory region code and I'm not
sure what is too be gained for the register code. The only usage of the
code is inside a loop in register_init_block32. In each case the region
has the same set of ops. Why isn't a single region being created with an
indirect handler which can dispatch to the individual register handling
code?
While its true some drivers create individual IO regions by an large
most are creating a block with a common handler.
> /**
> * memory_region_add_subregion_overlap: Add a subregion to a container
> * with overlap.
> diff --git a/memory.c b/memory.c
> index 09041ed..228a8a7 100644
> --- a/memory.c
> +++ b/memory.c
> @@ -1829,6 +1829,14 @@ void memory_region_add_subregion(MemoryRegion *mr,
> memory_region_add_subregion_common(mr, offset, subregion);
> }
>
> +void memory_region_add_subregion_no_print(MemoryRegion *mr,
> + hwaddr offset,
> + MemoryRegion *subregion)
> +{
> + memory_region_add_subregion(mr, offset, subregion);
> + subregion->do_not_print = true;
> +}
> +
> void memory_region_add_subregion_overlap(MemoryRegion *mr,
> hwaddr offset,
> MemoryRegion *subregion,
> @@ -2219,7 +2227,7 @@ static void mtree_print_mr(fprintf_function mon_printf, void *f,
> const MemoryRegion *submr;
> unsigned int i;
>
> - if (!mr) {
> + if (!mr || mr->do_not_print) {
> return;
> }
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree
2016-02-26 16:51 ` Alex Bennée
@ 2016-02-26 16:54 ` Peter Maydell
2016-03-08 0:49 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Peter Maydell @ 2016-02-26 16:54 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, QEMU Developers, Alistair Francis,
Peter Crosthwaite, Edgar E. Iglesias, Andreas Färber,
KONRAD Frédéric
On 26 February 2016 at 16:51, Alex Bennée <alex.bennee@linaro.org> wrote:
> I think this needlessly complicates the memory region code and I'm not
> sure what is too be gained for the register code. The only usage of the
> code is inside a loop in register_init_block32. In each case the region
> has the same set of ops. Why isn't a single region being created with an
> indirect handler which can dispatch to the individual register handling
> code?
>
> While its true some drivers create individual IO regions by an large
> most are creating a block with a common handler.
Yeah, I have to say I'm not really convinced about having one MR
per register -- the MR code was never intended to be used that way,
and it seems like a good way to find nasty performance or memory
usage surprises.
thanks
-- PMM
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 02/16] register: Add Register API
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 02/16] register: Add Register API Alistair Francis
@ 2016-02-26 17:13 ` Alex Bennée
2016-03-08 0:54 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-26 17:13 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> This API provides some encapsulation of registers and factors our some
> common functionality to common code. Bits of device state (usually MMIO
> registers), often have all sorts of access restrictions and semantics
> associated with them. This API allow you to define what those
> restrictions are on a bit-by-bit basis.
>
> Helper functions are then used to access the register which observe the
> semantics defined by the RegisterAccessInfo struct.
>
> Some features:
> Bits can be marked as read_only (ro field)
> Bits can be marked as write-1-clear (w1c field)
> Bits can be marked as reserved (rsvd field)
> Reset values can be defined (reset)
> Bits can throw guest errors when written certain values (ge0, ge1)
> Bits can throw unimp errors when written certain values (ui0, ui1)
> Bits can be marked clear on read (cor)
> Pre and post action callbacks can be added to read and write ops
> Verbose debugging info can be enabled/disabled
>
> Useful for defining device register spaces in a data driven way. Cuts
> down on a lot of the verbosity and repetition in the switch-case blocks
> in the standard foo_mmio_read/write functions.
>
> Also useful for automated generation of device models from hardware
> design sources.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V4:
> - Rebase
> - Remove the guest error masking
> - Simplify the unimplemented masking
> - Use the reserved value in the write calculations
> - Remove read_lite and write_lite
> - General fixes to asserts and log printing
> V3:
> - Address some comments from Fred
>
> hw/core/Makefile.objs | 1 +
> hw/core/register.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/register.h | 111 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 264 insertions(+)
> create mode 100644 hw/core/register.c
> create mode 100644 include/hw/register.h
>
> diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
> index abb3560..bf95db5 100644
> --- a/hw/core/Makefile.objs
> +++ b/hw/core/Makefile.objs
> @@ -14,4 +14,5 @@ common-obj-$(CONFIG_SOFTMMU) += machine.o
> common-obj-$(CONFIG_SOFTMMU) += null-machine.o
> common-obj-$(CONFIG_SOFTMMU) += loader.o
> common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
> +common-obj-$(CONFIG_SOFTMMU) += register.o
> common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o
> diff --git a/hw/core/register.c b/hw/core/register.c
> new file mode 100644
> index 0000000..7e47df5
> --- /dev/null
> +++ b/hw/core/register.c
> @@ -0,0 +1,152 @@
> +/*
> + * Register Definition API
> + *
> + * Copyright (c) 2013 Xilinx Inc.
> + * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2. See
> + * the COPYING file in the top-level directory.
> + */
> +
> +#include "hw/register.h"
> +#include "hw/qdev.h"
> +#include "qemu/log.h"
> +
> +static inline void register_write_log(int mask, RegisterInfo *reg, int dir,
> + uint64_t val, const char *msg,
> + const char *reason)
> +{
> + qemu_log_mask(mask, "%s:%s bits %#" PRIx64 " %s write of %d%s%s\n",
> + reg->prefix, reg->access->name, val, msg, dir,
> + reason ? ": " : "", reason ? reason : "");
> +}
This seems unused, I guess the compiler ignores unused inlines through :-/
> +
> +static inline void register_write_val(RegisterInfo *reg, uint64_t val)
> +{
> + g_assert(reg->data);
> +
> + switch (reg->data_size) {
> + case 1:
> + *(uint8_t *)reg->data = val;
> + break;
> + case 2:
> + *(uint16_t *)reg->data = val;
> + break;
> + case 4:
> + *(uint32_t *)reg->data = val;
> + break;
> + case 8:
> + *(uint64_t *)reg->data = val;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static inline uint64_t register_read_val(RegisterInfo *reg)
> +{
> + switch (reg->data_size) {
> + case 1:
> + return *(uint8_t *)reg->data;
> + case 2:
> + return *(uint16_t *)reg->data;
> + case 4:
> + return *(uint32_t *)reg->data;
> + case 8:
> + return *(uint64_t *)reg->data;
> + default:
> + g_assert_not_reached();
> + }
> + return 0; /* unreachable */
> +}
> +
> +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we)
> +{
> + uint64_t old_val, new_val, test, no_w_mask;
> + const RegisterAccessInfo *ac;
> +
> + assert(reg);
> +
> + ac = reg->access;
> +
> + if (!ac || !ac->name) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
> + "(written value: %#" PRIx64 ")\n", reg->prefix, val);
> + return;
> + }
> +
> + old_val = reg->data ? register_read_val(reg) : ac->reset;
> +
> + test = (old_val ^ val) & ac->rsvd;
> + if (test) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit"
> + "fields: %#" PRIx64 ")\n", reg->prefix, test);
> + }
> +
> + test = val & ac->unimp;
> + if (test) {
> + qemu_log_mask(LOG_UNIMP,
> + "%s:%s writing %#" PRIx64 " to unimplemented bits:" \
> + " %#" PRIx64 "",
> + reg->prefix, reg->access->name, val, ac->unimp);
> + }
> +
> +
> + no_w_mask = ac->ro | ac->w1c | ac->rsvd | ~we;
> + new_val = (val & ~no_w_mask) | (old_val & no_w_mask);
> + new_val &= ~(val & ac->w1c);
A comment wouldn't go amiss here describing the concatenation of
restrictions, RAZ, and ROW bits.
> +
> + if (ac->pre_write) {
> + new_val = ac->pre_write(reg, new_val);
> + }
> +
> + if (reg->debug) {
> + qemu_log("%s:%s: write of value %#" PRIx64 "\n", reg->prefix, ac->name,
> + new_val);
> + }
> +
> + register_write_val(reg, new_val);
> +
> + if (ac->post_write) {
> + ac->post_write(reg, new_val);
> + }
> +}
> +
> +uint64_t register_read(RegisterInfo *reg)
> +{
> + uint64_t ret;
> + const RegisterAccessInfo *ac;
> +
> + assert(reg);
> +
> + ac = reg->access;
> + if (!ac || !ac->name) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: read from undefined device state\n",
> + reg->prefix);
> + return 0;
> + }
> +
> + ret = reg->data ? register_read_val(reg) : ac->reset;
> +
> + register_write_val(reg, ret & ~ac->cor);
> +
> + if (ac->post_read) {
> + ret = ac->post_read(reg, ret);
> + }
> +
> + if (reg->debug) {
> + qemu_log("%s:%s: read of value %#" PRIx64 "\n", reg->prefix,
> + ac->name, ret);
> + }
> +
> + return ret;
> +}
> +
> +void register_reset(RegisterInfo *reg)
> +{
> + g_assert(reg);
> + g_assert(reg->data);
> + g_assert(reg->access);
> +
> + register_write_val(reg, reg->access->reset);
> +}
> diff --git a/include/hw/register.h b/include/hw/register.h
> new file mode 100644
> index 0000000..444239c
> --- /dev/null
> +++ b/include/hw/register.h
> @@ -0,0 +1,111 @@
> +/*
> + * Register Definition API
> + *
> + * Copyright (c) 2013 Xilinx Inc.
> + * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2. See
> + * the COPYING file in the top-level directory.
> + */
> +
> +#ifndef REGISTER_H
> +#define REGISTER_H
> +
> +#include "exec/memory.h"
> +
> +typedef struct RegisterInfo RegisterInfo;
> +typedef struct RegisterAccessInfo RegisterAccessInfo;
> +
> +/**
> + * Access description for a register that is part of guest accessible device
> + * state.
> + *
> + * @name: String name of the register
> + * @ro: whether or not the bit is read-only
> + * @w1c: bits with the common write 1 to clear semantic.
> + * @reset: reset value.
> + * @cor: Bits that are clear on read
> + * @rsvd: Bits that are reserved and should not be changed
> + *
> + * @ui1: Bits that when written 1 indicate use of an unimplemented feature
> + * @ui0: Bits that when written 0 indicate use of an unimplemented
> feature
Last two comments don't match actual definition.
> + *
> + * @pre_write: Pre write callback. Passed the value that's to be written,
> + * immediately before the actual write. The returned value is what is written,
> + * giving the handler a chance to modify the written value.
> + * @post_write: Post write callback. Passed the written value. Most write side
> + * effects should be implemented here.
> + *
> + * @post_read: Post read callback. Passes the value that is about to be returned
> + * for a read. The return value from this function is what is ultimately read,
> + * allowing this function to modify the value before return to the client.
> + */
> +
> +struct RegisterAccessInfo {
> + const char *name;
> + uint64_t ro;
> + uint64_t w1c;
> + uint64_t reset;
> + uint64_t cor;
> + uint64_t rsvd;
> + uint64_t unimp;
> +
> + uint64_t (*pre_write)(RegisterInfo *reg, uint64_t val);
> + void (*post_write)(RegisterInfo *reg, uint64_t val);
> +
> + uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
> +};
> +
> +/**
> + * A register that is part of guest accessible state
> + * @data: pointer to the register data. Will be cast
> + * to the relevant uint type depending on data_size.
> + * @data_size: Size of the register in bytes. Must be
> + * 1, 2, 4 or 8
> + *
> + * @access: Access description of this register
> + *
> + * @debug: Whether or not verbose debug is enabled
> + * @prefix: String prefix for log and debug messages
> + *
> + * @opaque: Opaque data for the register
> + */
> +
> +struct RegisterInfo {
> + /* <public> */
> + void *data;
> + int data_size;
> +
> + const RegisterAccessInfo *access;
> +
> + bool debug;
> + const char *prefix;
> +
> + void *opaque;
> +};
> +
> +/**
> + * write a value to a register, subject to its restrictions
> + * @reg: register to write to
> + * @val: value to write
> + * @we: write enable mask
> + */
> +
> +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we);
> +
> +/**
> + * read a value from a register, subject to its restrictions
> + * @reg: register to read from
> + * returns: value read
> + */
> +
> +uint64_t register_read(RegisterInfo *reg);
> +
> +/**
> + * reset a register
> + * @reg: register to reset
> + */
> +
> +void register_reset(RegisterInfo *reg);
> +
> +#endif
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 03/16] register: Add Memory API glue
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 03/16] register: Add Memory API glue Alistair Francis
@ 2016-02-26 17:25 ` Alex Bennée
2016-03-08 1:18 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-26 17:25 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Add memory io handlers that glue the register API to the memory API.
> Just translation functions at this stage. Although it does allow for
> devices to be created without all-in-one mmio r/w handlers.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> hw/core/register.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/register.h | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
>
> diff --git a/hw/core/register.c b/hw/core/register.c
> index 7e47df5..9cd50c8 100644
> --- a/hw/core/register.c
> +++ b/hw/core/register.c
> @@ -150,3 +150,51 @@ void register_reset(RegisterInfo *reg)
>
> register_write_val(reg, reg->access->reset);
> }
> +
> +static inline void register_write_memory(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size, bool be)
> +{
> + RegisterInfo *reg = opaque;
> + uint64_t we = ~0;
> + int shift = 0;
> +
> + if (reg->data_size != size) {
> + we = (size == 8) ? ~0ull : (1ull << size * 8) - 1;
> + shift = 8 * (be ? reg->data_size - size - addr : addr);
> + }
What happens if the user writes too large a value at once to the
register? I haven't attempted to decode the shift magic going on here
but perhaps the handling would be clearer if there was a:
if (size > reg->data_size) {
..deal with it..
} else if (size < data_size ) {
..do other magic..
}
> +
> + assert(size + addr <= reg->data_size);
Why are we asserting expected input conditions after we've done stuff?
> + register_write(reg, value << shift, we << shift);
> +}
> +
> +void register_write_memory_be(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + register_write_memory(opaque, addr, value, size, true);
> +}
> +
> +
> +void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + register_write_memory(opaque, addr, value, size, false);
> +}
> +
> +static inline uint64_t register_read_memory(void *opaque, hwaddr addr,
> + unsigned size, bool be)
> +{
> + RegisterInfo *reg = opaque;
> + int shift = 8 * (be ? reg->data_size - size - addr : addr);
> +
Well we never have to deal with an over/undersized read? I suspect the
magic above might not correctly represent some hardware when presented
with such a thing on the bus.
> + return register_read(reg) >> shift;
> +}
> +
> +uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size)
> +{
> + return register_read_memory(opaque, addr, size, true);
> +}
> +
> +uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size)
> +{
> + return register_read_memory(opaque, addr, size, false);
> +}
> diff --git a/include/hw/register.h b/include/hw/register.h
> index 444239c..9aa9cfc 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -69,9 +69,14 @@ struct RegisterAccessInfo {
> * @prefix: String prefix for log and debug messages
> *
> * @opaque: Opaque data for the register
> + *
> + * @mem: optional Memory region for the register
> */
>
> struct RegisterInfo {
> + /* <private> */
> + MemoryRegion mem;
> +
This seems unconnected with adding the helpers. Should it come with the
original definition or when it actually gets used?
> /* <public> */
> void *data;
> int data_size;
> @@ -108,4 +113,30 @@ uint64_t register_read(RegisterInfo *reg);
>
> void register_reset(RegisterInfo *reg);
>
> +/**
> + * Memory API MMIO write handler that will write to a Register API register.
> + * _be for big endian variant and _le for little endian.
> + * @opaque: RegisterInfo to write to
> + * @addr: Address to write
> + * @value: Value to write
> + * @size: Number of bytes to write
> + */
> +
> +void register_write_memory_be(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size);
> +void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size);
> +
> +/**
> + * Memory API MMIO read handler that will read from a Register API register.
> + * _be for big endian variant and _le for little endian.
> + * @opaque: RegisterInfo to read from
> + * @addr: Address to read
> + * @size: Number of bytes to read
> + * returns: Value read from register
> + */
> +
> +uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size);
> +uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size);
> +
> #endif
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper Alistair Francis
@ 2016-02-29 11:28 ` Alex Bennée
2016-03-08 0:09 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-29 11:28 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Add a helper that will scan a static RegisterAccessInfo Array
> and populate a container MemoryRegion with registers as defined.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V3:
> - Fix typo
> V2:
> - Use memory_region_add_subregion_no_print()
>
> hw/core/register.c | 29 +++++++++++++++++++++++++++++
> include/hw/register.h | 20 ++++++++++++++++++++
> 2 files changed, 49 insertions(+)
>
> diff --git a/hw/core/register.c b/hw/core/register.c
> index d766517..ac866f6 100644
> --- a/hw/core/register.c
> +++ b/hw/core/register.c
> @@ -210,6 +210,35 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size)
> return register_read_memory(opaque, addr, size, false);
> }
>
> +void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
> + int num, RegisterInfo *ri, uint32_t *data,
> + MemoryRegion *container, const MemoryRegionOps *ops,
> + bool debug_enabled)
> +{
> + const char *debug_prefix = object_get_typename(OBJECT(owner));
> + int i;
> +
> + for (i = 0; i < num; i++) {
> + int index = rae[i].decode.addr / 4;
> + RegisterInfo *r = &ri[index];
> +
> + *r = (RegisterInfo) {
> + .data = &data[index],
> + .data_size = sizeof(uint32_t),
> + .access = &rae[i],
> + .debug = debug_enabled,
> + .prefix = debug_prefix,
> + .opaque = owner,
> + };
> + register_init(r);
> +
> + memory_region_init_io(&r->mem, OBJECT(owner), ops, r, r->access->name,
> + sizeof(uint32_t));
> + memory_region_add_subregion_no_print(container,
> + r->access->decode.addr,
> &r->mem);
As I mentioned in the previous patch I think having a subregion
per-register is excessive. I think you need single io region with the
private data giving a structure with the list of registers in the block.
You can then have a general purpose set of register ops to lookup the
eventual register and dispatch to the handler.
> + }
> +}
> +
> static const TypeInfo register_info = {
> .name = TYPE_REGISTER,
> .parent = TYPE_DEVICE,
> diff --git a/include/hw/register.h b/include/hw/register.h
> index d3469c6..6ac005c 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -162,6 +162,26 @@ void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
> uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size);
> uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size);
>
> +/**
> + * Init a block of consecutive registers into a container MemoryRegion. A
> + * number of constant register definitions are parsed to create a corresponding
> + * array of RegisterInfo's.
> + *
> + * @owner: device owning the registers
> + * @rae: Register definitions to init
> + * @num: number of registers to init (length of @rae)
> + * @ri: Register array to init
> + * @data: Array to use for register data
> + * @container: Memory region to contain new registers
> + * @ops: Memory region ops to access registers.
> + * @debug enabled: turn on/off verbose debug information
> + */
> +
> +void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
> + int num, RegisterInfo *ri, uint32_t *data,
> + MemoryRegion *container, const MemoryRegionOps *ops,
> + bool debug_enabled);
> +
> /* Define constants for a 32 bit register */
> #define REG32(reg, addr) \
> enum { A_ ## reg = (addr) }; \
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro Alistair Francis
@ 2016-02-29 11:51 ` Alex Bennée
2016-03-04 22:42 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-29 11:51 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Little macro that just gives you N ones (justified to LSB).
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> include/qemu/bitops.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
> index 8164225..27bf98d 100644
> --- a/include/qemu/bitops.h
> +++ b/include/qemu/bitops.h
> @@ -430,4 +430,6 @@ static inline uint64_t deposit64(uint64_t value, int start, int length,
> return (value & ~mask) | ((fieldval << start) & mask);
> }
>
> +#define ONES(num) ((num) == 64 ? ~0ull : (1ull << (num)) - 1)
> +
I'm a little ambivalent about this one. The definition should probably
be up at the top of the file with the other #defines. I don't like the
name as it is a little too generic. I also notice in all the actual uses
you immediately invert the result because you want to mask the top bits.
I suspect what's needed here is a more generic helper:
#define MAKE_64BIT_MASK (shift, length) \
...
And then the:
.ro = ~ONES(27) },
Becomes:
.ro = MAKE_64BIT_MASK(27, 64 - 27);
> #endif
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model Alistair Francis
@ 2016-02-29 12:20 ` Alex Bennée
2016-03-04 19:41 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-29 12:20 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Minimal device model for devcfg module of Zynq. DMA capabilities and
> interrupt generation supported.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> default-configs/arm-softmmu.mak | 1 +
> hw/dma/Makefile.objs | 1 +
> hw/dma/xlnx-zynq-devcfg.c | 397 ++++++++++++++++++++++++++++++++++++++
> include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
> 4 files changed, 461 insertions(+)
> create mode 100644 hw/dma/xlnx-zynq-devcfg.c
> create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index a9f82a1..d524584 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -66,6 +66,7 @@ CONFIG_PXA2XX=y
> CONFIG_BITBANG_I2C=y
> CONFIG_FRAMEBUFFER=y
> CONFIG_XILINX_SPIPS=y
> +CONFIG_ZYNQ_DEVCFG=y
>
> CONFIG_ARM11SCU=y
> CONFIG_A9SCU=y
> diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
> index 0e65ed0..eaf0a81 100644
> --- a/hw/dma/Makefile.objs
> +++ b/hw/dma/Makefile.objs
> @@ -5,6 +5,7 @@ common-obj-$(CONFIG_PL330) += pl330.o
> common-obj-$(CONFIG_I82374) += i82374.o
> common-obj-$(CONFIG_I8257) += i8257.o
> common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
> +common-obj-$(CONFIG_ZYNQ_DEVCFG) += xlnx-zynq-devcfg.o
> common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
> common-obj-$(CONFIG_STP2000) += sparc32_dma.o
> common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
> new file mode 100644
> index 0000000..0420123
> --- /dev/null
> +++ b/hw/dma/xlnx-zynq-devcfg.c
> @@ -0,0 +1,397 @@
> +/*
> + * QEMU model of the Xilinx Zynq Devcfg Interface
> + *
> + * (C) 2011 PetaLogix Pty Ltd
> + * (C) 2014 Xilinx Inc.
> + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/dma/xlnx-zynq-devcfg.h"
> +#include "qemu/bitops.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/dma.h"
> +
> +#define FREQ_HZ 900000000
> +
> +#define BTT_MAX 0x400
> +
> +#ifndef XLNX_ZYNQ_DEVCFG_ERR_DEBUG
> +#define XLNX_ZYNQ_DEVCFG_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT(...) do { \
> + if (XLNX_ZYNQ_DEVCFG_ERR_DEBUG) { \
> + qemu_log("%s: ", __func__); \
> + qemu_log(__VA_ARGS__); \
> + } \
> +} while (0);
This can be done in one qemu_log invocation as per other patches.
> +
> +REG32(CTRL, 0x00)
> + FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */
> + FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
> + FIELD(CTRL, PCAP_MODE, 26, 1)
> + FIELD(CTRL, MULTIBOOT_EN, 24, 1)
> + FIELD(CTRL, USER_MODE, 15, 1)
> + FIELD(CTRL, PCFG_AES_FUSE, 12, 1)
> + FIELD(CTRL, PCFG_AES_EN, 9, 3)
> + FIELD(CTRL, SEU_EN, 8, 1)
> + FIELD(CTRL, SEC_EN, 7, 1)
> + FIELD(CTRL, SPNIDEN, 6, 1)
> + FIELD(CTRL, SPIDEN, 5, 1)
> + FIELD(CTRL, NIDEN, 4, 1)
> + FIELD(CTRL, DBGEN, 3, 1)
> + FIELD(CTRL, DAP_EN, 0, 3)
> +
> +REG32(LOCK, 0x04)
> + #define AES_FUSE_LOCK 4
> + #define AES_EN_LOCK 3
> + #define SEU_LOCK 2
> + #define SEC_LOCK 1
> + #define DBG_LOCK 0
> +
> +/* mapping bits in R_LOCK to what they lock in R_CTRL */
> +static const uint32_t lock_ctrl_map[] = {
> + [AES_FUSE_LOCK] = R_CTRL_PCFG_AES_FUSE_MASK,
> + [AES_EN_LOCK] = R_CTRL_PCFG_AES_EN_MASK,
> + [SEU_LOCK] = R_CTRL_SEU_EN_MASK,
> + [SEC_LOCK] = R_CTRL_SEC_EN_MASK,
> + [DBG_LOCK] = R_CTRL_SPNIDEN_MASK | R_CTRL_SPIDEN_MASK |
> + R_CTRL_NIDEN_MASK | R_CTRL_DBGEN_MASK |
> + R_CTRL_DAP_EN_MASK,
> +};
> +
> +REG32(CFG, 0x08)
> + FIELD(CFG, RFIFO_TH, 10, 2)
> + FIELD(CFG, WFIFO_TH, 8, 2)
> + FIELD(CFG, RCLK_EDGE, 7, 1)
> + FIELD(CFG, WCLK_EDGE, 6, 1)
> + FIELD(CFG, DISABLE_SRC_INC, 5, 1)
> + FIELD(CFG, DISABLE_DST_INC, 4, 1)
> +#define R_CFG_RO 0xFFFFF000
If this was:
FIELD(CFG, RO, 12, 20)
Wouldn't you get:
R_CFG_RO_MASK for free?
> +#define R_CFG_RESET 0x50B
> +
> +REG32(INT_STS, 0x0C)
> + FIELD(INT_STS, PSS_GTS_USR_B, 31, 1)
> + FIELD(INT_STS, PSS_FST_CFG_B, 30, 1)
> + FIELD(INT_STS, PSS_CFG_RESET_B, 27, 1)
> + FIELD(INT_STS, RX_FIFO_OV, 18, 1)
> + FIELD(INT_STS, WR_FIFO_LVL, 17, 1)
> + FIELD(INT_STS, RD_FIFO_LVL, 16, 1)
> + FIELD(INT_STS, DMA_CMD_ERR, 15, 1)
> + FIELD(INT_STS, DMA_Q_OV, 14, 1)
> + FIELD(INT_STS, DMA_DONE, 13, 1)
> + FIELD(INT_STS, DMA_P_DONE, 12, 1)
> + FIELD(INT_STS, P2D_LEN_ERR, 11, 1)
> + FIELD(INT_STS, PCFG_DONE, 2, 1)
> + #define R_INT_STS_RSVD ((0x7 << 24) | (0x1 << 19) | (0xF < 7))
> +
> +REG32(INT_MASK, 0x10)
> +
> +REG32(STATUS, 0x14)
> + FIELD(STATUS, DMA_CMD_Q_F, 31, 1)
> + FIELD(STATUS, DMA_CMD_Q_E, 30, 1)
> + FIELD(STATUS, DMA_DONE_CNT, 28, 2)
> + FIELD(STATUS, RX_FIFO_LVL, 20, 5)
> + FIELD(STATUS, TX_FIFO_LVL, 12, 7)
> + FIELD(STATUS, PSS_GTS_USR_B, 11, 1)
> + FIELD(STATUS, PSS_FST_CFG_B, 10, 1)
> + FIELD(STATUS, PSS_CFG_RESET_B, 5, 1)
> +
> +REG32(DMA_SRC_ADDR, 0x18)
> +REG32(DMA_DST_ADDR, 0x1C)
> +REG32(DMA_SRC_LEN, 0x20)
> +REG32(DMA_DST_LEN, 0x24)
> +REG32(ROM_SHADOW, 0x28)
> +REG32(SW_ID, 0x30)
> +REG32(UNLOCK, 0x34)
> +
> +#define R_UNLOCK_MAGIC 0x757BDF0D
> +
> +REG32(MCTRL, 0x80)
> + FIELD(MCTRL, PS_VERSION, 28, 4)
> + FIELD(MCTRL, PCFG_POR_B, 8, 1)
> + FIELD(MCTRL, INT_PCAP_LPBK, 4, 1)
> + FIELD(MCTRL, QEMU, 3, 1)
> +
> +static void xlnx_zynq_devcfg_update_ixr(XlnxZynqDevcfg *s)
> +{
> + qemu_set_irq(s->irq, ~s->regs[R_INT_MASK] & s->regs[R_INT_STS]);
What defines R_INT_MASK? It looks as though only FIELD() definitions
give R_reg_field_MASK defines?
This is the problem with the "auto-magic" derived names. If I grep the
source code for R_INT_MASK I only find the use. Actually now I realise
that INT_MASK is a register name not a field. I think we need access
helpers to guide the user. ~s->regs[GET_REG_NUM(INT_MASK)] would prompt
the user to search for INT_MASK to find the original definitions.
> +}
> +
> +static void xlnx_zynq_devcfg_reset(DeviceState *dev)
> +{
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(dev);
> + int i;
> +
> + for (i = 0; i < XLNX_ZYNQ_DEVCFG_R_MAX; ++i) {
> + register_reset(&s->regs_info[i]);
> + }
> +}
> +
> +static void xlnx_zynq_devcfg_dma_go(XlnxZynqDevcfg *s)
> +{
> + for (;;) {
> + uint8_t buf[BTT_MAX];
> + XlnxZynqDevcfgDMACmd *dmah = s->dma_cmd_fifo;
> + uint32_t btt = BTT_MAX;
> + bool loopback = s->regs[R_MCTRL] & R_MCTRL_INT_PCAP_LPBK_MASK;
> +
> + btt = MIN(btt, dmah->src_len);
> + if (loopback) {
> + btt = MIN(btt, dmah->dest_len);
> + }
> + DB_PRINT("reading %x bytes from %x\n", btt, dmah->src_addr);
> + dma_memory_read(&address_space_memory, dmah->src_addr, buf, btt);
> + dmah->src_len -= btt;
> + dmah->src_addr += btt;
> + if (loopback) {
> + DB_PRINT("writing %x bytes from %x\n", btt, dmah->dest_addr);
> + dma_memory_write(&address_space_memory, dmah->dest_addr, buf, btt);
> + dmah->dest_len -= btt;
> + dmah->dest_addr += btt;
> + }
> + if (!dmah->src_len && !dmah->dest_len) {
> + DB_PRINT("dma operation finished\n");
> + s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
> + R_INT_STS_DMA_P_DONE_MASK;
> + s->dma_cmd_fifo_num--;
> + memmove(s->dma_cmd_fifo, &s->dma_cmd_fifo[1],
> + sizeof(*s->dma_cmd_fifo) * XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN
> + - 1);
> + }
> + xlnx_zynq_devcfg_update_ixr(s);
> + if (!s->dma_cmd_fifo_num) { /* All done */
> + return;
> + }
> + }
I noticed this before in other patches I think. I guess it is a
stylistic choice but certainly for a single well defined end condition
do () while {} reads more naturally.
> +}
> +
> +static void r_ixr_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
> +
> + xlnx_zynq_devcfg_update_ixr(s);
> +}
> +
> +static uint64_t r_ctrl_pre_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(lock_ctrl_map); ++i) {
> + if (s->regs[R_LOCK] & 1 << i) {
> + val &= ~lock_ctrl_map[i];
> + val |= lock_ctrl_map[i] & s->regs[R_CTRL];
> + }
> + }
> + return val;
> +}
> +
> +static void r_ctrl_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + uint32_t aes_en = F_EX32(val, CTRL, PCFG_AES_EN);
> +
> + if (aes_en != 0 && aes_en != 7) {
> + qemu_log_mask(LOG_UNIMP, "%s: warning, aes-en bits inconsistent,"
> + "unimplemented security reset should happen!\n",
> + reg->prefix);
> + }
> +}
> +
> +static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
> +
> + if (val == R_UNLOCK_MAGIC) {
> + DB_PRINT("successful unlock\n");
> + /* BootROM will have already done the actual unlock so no need to do
> + * anything in successful subsequent unlock
> + */
> + } else { /* bad unlock attempt */
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: failed unlock\n", reg->prefix);
> + s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK;
> + s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK;
> + /* core becomes inaccessible */
> + memory_region_set_enabled(&s->iomem, false);
> + }
> +}
> +
> +static uint64_t r_lock_pre_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
> +
> + /* once bits are locked they stay locked */
> + return s->regs[R_LOCK] | val;
> +}
> +
> +static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
> +
> + s->dma_cmd_fifo[s->dma_cmd_fifo_num] = (XlnxZynqDevcfgDMACmd) {
> + .src_addr = s->regs[R_DMA_SRC_ADDR] & ~0x3UL,
> + .dest_addr = s->regs[R_DMA_DST_ADDR] & ~0x3UL,
> + .src_len = s->regs[R_DMA_SRC_LEN] << 2,
> + .dest_len = s->regs[R_DMA_DST_LEN] << 2,
> + };
> + s->dma_cmd_fifo_num++;
> + DB_PRINT("dma transfer started; %d total transfers pending\n",
> + s->dma_cmd_fifo_num);
> + xlnx_zynq_devcfg_dma_go(s);
> +}
> +
> +static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
> + { .name = "CTRL", .decode.addr = A_CTRL,
> + .reset = R_CTRL_PCAP_PR_MASK | R_CTRL_PCAP_MODE_MASK | 0x3 << 13,
> + .rsvd = 0x1 << 28 | 0x3ff << 13 | 0x3 << 13,
> + .pre_write = r_ctrl_pre_write,
> + .post_write = r_ctrl_post_write,
> + },
> + { .name = "LOCK", .decode.addr = A_LOCK,
The same comment can be mode for the automagic addresses.
GET_REG_ADDR(LOCK) would be clearer.
> + .rsvd = ~ONES(5),
> + .pre_write = r_lock_pre_write,
> + },
> + { .name = "CFG", .decode.addr = A_CFG,
> + .reset = 1 << R_CFG_RFIFO_TH_SHIFT | 1 << R_CFG_WFIFO_TH_SHIFT | 0x8,
> + .rsvd = 0xfffff00f,
> + },
> + { .name = "INT_STS", .decode.addr = A_INT_STS,
> + .w1c = ~R_INT_STS_RSVD,
> + .reset = R_INT_STS_PSS_GTS_USR_B_MASK |
> + R_INT_STS_PSS_CFG_RESET_B_MASK |
> + R_INT_STS_WR_FIFO_LVL_MASK,
> + .rsvd = R_INT_STS_RSVD,
> + .post_write = r_ixr_post_write,
> + },
> + { .name = "INT_MASK", .decode.addr = A_INT_MASK,
> + .reset = ~0,
> + .rsvd = R_INT_STS_RSVD,
> + .post_write = r_ixr_post_write,
> + },
> + { .name = "STATUS", .decode.addr = A_STATUS,
> + .reset = R_STATUS_DMA_CMD_Q_E_MASK |
> + R_STATUS_PSS_GTS_USR_B_MASK |
> + R_STATUS_PSS_CFG_RESET_B_MASK,
> + .ro = ~0,
> + },
> + { .name = "DMA_SRC_ADDR", .decode.addr = A_DMA_SRC_ADDR, },
> + { .name = "DMA_DST_ADDR", .decode.addr = A_DMA_DST_ADDR, },
> + { .name = "DMA_SRC_LEN", .decode.addr = A_DMA_SRC_LEN,
> + .ro = ~ONES(27) },
> + { .name = "DMA_DST_LEN", .decode.addr = A_DMA_DST_LEN,
> + .ro = ~ONES(27),
> + .post_write = r_dma_dst_len_post_write,
> + },
> + { .name = "ROM_SHADOW", .decode.addr = A_ROM_SHADOW,
> + .rsvd = ~0ull,
> + },
> + { .name = "SW_ID", .decode.addr = A_SW_ID, },
> + { .name = "UNLOCK", .decode.addr = A_UNLOCK,
> + .post_write = r_unlock_post_write,
> + },
> + { .name = "MCTRL", .decode.addr = R_MCTRL * 4,
> + /* Silicon 3.0 for version field, the mysterious reserved bit 23
> + * and QEMU platform identifier.
> + */
> + .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU_MASK,
> + .ro = ~R_MCTRL_INT_PCAP_LPBK_MASK,
> + .rsvd = 0x00f00303,
> + },
> +};
> +
> +static const MemoryRegionOps xlnx_zynq_devcfg_reg_ops = {
> + .read = register_read_memory_le,
> + .write = register_write_memory_le,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + }
> +};
> +
> +static const VMStateDescription vmstate_xlnx_zynq_devcfg_dma_cmd = {
> + .name = "xlnx_zynq_devcfg_dma_cmd",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(src_addr, XlnxZynqDevcfgDMACmd),
> + VMSTATE_UINT32(dest_addr, XlnxZynqDevcfgDMACmd),
> + VMSTATE_UINT32(src_len, XlnxZynqDevcfgDMACmd),
> + VMSTATE_UINT32(dest_len, XlnxZynqDevcfgDMACmd),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static const VMStateDescription vmstate_xlnx_zynq_devcfg = {
> + .name = "xlnx_zynq_devcfg",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_STRUCT_ARRAY(dma_cmd_fifo, XlnxZynqDevcfg,
> + XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN, 0,
> + vmstate_xlnx_zynq_devcfg_dma_cmd,
> + XlnxZynqDevcfgDMACmd),
> + VMSTATE_UINT8(dma_cmd_fifo_num, XlnxZynqDevcfg),
> + VMSTATE_UINT32_ARRAY(regs, XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG_R_MAX),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void xlnx_zynq_devcfg_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(obj);
> +
> + sysbus_init_irq(sbd, &s->irq);
> +
> + memory_region_init(&s->iomem, obj, "devcfg", XLNX_ZYNQ_DEVCFG_R_MAX * 4);
> + register_init_block32(DEVICE(obj), xlnx_zynq_devcfg_regs_info,
> + ARRAY_SIZE(xlnx_zynq_devcfg_regs_info),
> + s->regs_info, s->regs, &s->iomem,
> + &xlnx_zynq_devcfg_reg_ops,
> + XLNX_ZYNQ_DEVCFG_ERR_DEBUG);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static void xlnx_zynq_devcfg_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->reset = xlnx_zynq_devcfg_reset;
> + dc->vmsd = &vmstate_xlnx_zynq_devcfg;
> +}
> +
> +static const TypeInfo xlnx_zynq_devcfg_info = {
> + .name = TYPE_XLNX_ZYNQ_DEVCFG,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XlnxZynqDevcfg),
> + .instance_init = xlnx_zynq_devcfg_init,
> + .class_init = xlnx_zynq_devcfg_class_init,
> +};
> +
> +static void xlnx_zynq_devcfg_register_types(void)
> +{
> + type_register_static(&xlnx_zynq_devcfg_info);
> +}
> +
> +type_init(xlnx_zynq_devcfg_register_types)
> diff --git a/include/hw/dma/xlnx-zynq-devcfg.h b/include/hw/dma/xlnx-zynq-devcfg.h
> new file mode 100644
> index 0000000..d40e5c8
> --- /dev/null
> +++ b/include/hw/dma/xlnx-zynq-devcfg.h
> @@ -0,0 +1,62 @@
> +/*
> + * QEMU model of the Xilinx Devcfg Interface
> + *
> + * (C) 2011 PetaLogix Pty Ltd
> + * (C) 2014 Xilinx Inc.
> + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef XLNX_ZYNQ_DEVCFG_H
> +
> +#include "hw/register.h"
> +#include "hw/sysbus.h"
> +
> +#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
> +
> +#define XLNX_ZYNQ_DEVCFG(obj) \
> + OBJECT_CHECK(XlnxZynqDevcfg, (obj), TYPE_XLNX_ZYNQ_DEVCFG)
> +
> +#define XLNX_ZYNQ_DEVCFG_R_MAX 0x118
> +
> +#define XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN 10
> +
> +typedef struct XlnxZynqDevcfgDMACmd {
> + uint32_t src_addr;
> + uint32_t dest_addr;
> + uint32_t src_len;
> + uint32_t dest_len;
> +} XlnxZynqDevcfgDMACmd;
> +
> +typedef struct XlnxZynqDevcfg {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> + qemu_irq irq;
> +
> + XlnxZynqDevcfgDMACmd dma_cmd_fifo[XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN];
> + uint8_t dma_cmd_fifo_num;
> +
> + uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
> + RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
> +} XlnxZynqDevcfg;
> +
> +#define XLNX_ZYNQ_DEVCFG_H
> +#endif
Sp having looked through the macro magic I'm happier with what it is
doing. Using accessors will help with the navigation though. The common
question someone looking over the code will want to answer is where is X
defined.
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API Alistair Francis
@ 2016-02-29 12:22 ` Alex Bennée
2016-03-04 18:47 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-29 12:22 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Add GPIO functionality to the register API. This allows association
> and automatic connection of GPIOs to bits in registers. GPIO inputs
> will attach to handlers that automatically set read-only bits in
> registers. GPIO outputs will be updated to reflect their field value
> when their respective registers are written (or reset). Supports
> active low GPIOs.
>
> This is particularly effective for implementing system level
> controllers, where heterogenous collections of control signals are
> placed is a SoC specific peripheral then propagated all over the
> system.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> [ EI Changes:
> * register: Add a polarity field to GPIO connections
> Makes it possible to directly connect active low signals
> to generic interrupt pins.
> ]
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> hw/core/register.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/register.h | 37 ++++++++++++++++++++
> 2 files changed, 133 insertions(+)
>
> diff --git a/hw/core/register.c b/hw/core/register.c
> index ac866f6..1dc7ccc 100644
> --- a/hw/core/register.c
> +++ b/hw/core/register.c
> @@ -106,6 +106,7 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we)
> }
>
> register_write_val(reg, new_val);
> + register_refresh_gpios(reg, old_val);
>
> if (ac->post_write) {
> ac->post_write(reg, new_val);
> @@ -147,19 +148,113 @@ void register_reset(RegisterInfo *reg)
> g_assert(reg);
> g_assert(reg->data);
> g_assert(reg->access);
> + uint64_t old_val;
> +
> + old_val = register_read_val(reg);
>
> register_write_val(reg, reg->access->reset);
> + register_refresh_gpios(reg, old_val);
> +}
> +
> +void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value)
> +{
> + const RegisterAccessInfo *ac;
> + const RegisterGPIOMapping *gpio;
> +
> + ac = reg->access;
> + for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
> + int i;
> +
> + if (gpio->input) {
> + continue;
> + }
> +
> + for (i = 0; i < gpio->num; ++i) {
> + uint64_t gpio_value, gpio_value_old;
> +
> + qemu_irq gpo = qdev_get_gpio_out_named(DEVICE(reg), gpio->name, i);
> + gpio_value_old = extract64(old_value,
> + gpio->bit_pos + i * gpio->width,
> + gpio->width) ^ gpio->polarity;
> + gpio_value = extract64(register_read_val(reg),
> + gpio->bit_pos + i * gpio->width,
> + gpio->width) ^ gpio->polarity;
> + if (!(gpio_value_old ^ gpio_value)) {
> + continue;
> + }
> + if (reg->debug && gpo) {
> + qemu_log("refreshing gpio out %s to %" PRIx64 "\n",
> + gpio->name, gpio_value);
> + }
> + qemu_set_irq(gpo, gpio_value);
> + }
> + }
> +}
> +
> +typedef struct DeviceNamedGPIOHandlerOpaque {
> + DeviceState *dev;
> + const char *name;
> +} DeviceNamedGPIOHandlerOpaque;
> +
> +static void register_gpio_handler(void *opaque, int n, int level)
> +{
> + DeviceNamedGPIOHandlerOpaque *gho = opaque;
> + RegisterInfo *reg = REGISTER(gho->dev);
> +
> + const RegisterAccessInfo *ac;
> + const RegisterGPIOMapping *gpio;
> +
> + ac = reg->access;
> + for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
> + if (gpio->input && !strcmp(gho->name, gpio->name)) {
> + register_write_val(reg, deposit64(register_read_val(reg),
> + gpio->bit_pos + n * gpio->width,
> + gpio->width,
> + level ^ gpio->polarity));
> + return;
> + }
> + }
> +
> + abort();
> }
>
> void register_init(RegisterInfo *reg)
> {
> assert(reg);
> + const RegisterAccessInfo *ac;
> + const RegisterGPIOMapping *gpio;
>
> if (!reg->data || !reg->access) {
> return;
> }
>
> object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER);
> +
> + ac = reg->access;
> + for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
> + if (!gpio->num) {
> + ((RegisterGPIOMapping *)gpio)->num = 1;
> + }
> + if (!gpio->width) {
> + ((RegisterGPIOMapping *)gpio)->width = 1;
> + }
> + if (gpio->input) {
> + DeviceNamedGPIOHandlerOpaque gho = {
> + .name = gpio->name,
> + .dev = DEVICE(reg),
> + };
> + qemu_irq irq;
> +
> + qdev_init_gpio_in_named(DEVICE(reg), register_gpio_handler,
> + gpio->name, gpio->num);
> + irq = qdev_get_gpio_in_named(DEVICE(reg), gpio->name, gpio->num);
> + qemu_irq_set_opaque(irq, g_memdup(&gho, sizeof(gho)));
> + } else {
> + qemu_irq *gpos = g_new0(qemu_irq, gpio->num);
> +
> + qdev_init_gpio_out_named(DEVICE(reg), gpos, gpio->name, gpio->num);
> + }
> + }
> }
>
> static inline void register_write_memory(void *opaque, hwaddr addr,
> @@ -231,6 +326,7 @@ void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
> .opaque = owner,
> };
> register_init(r);
> + qdev_pass_all_gpios(DEVICE(r), owner);
>
> memory_region_init_io(&r->mem, OBJECT(owner), ops, r, r->access->name,
> sizeof(uint32_t));
> diff --git a/include/hw/register.h b/include/hw/register.h
> index 6ac005c..4d284a9 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -13,11 +13,35 @@
>
> #include "hw/qdev-core.h"
> #include "exec/memory.h"
> +#include "hw/irq.h"
>
> typedef struct RegisterInfo RegisterInfo;
> typedef struct RegisterAccessInfo RegisterAccessInfo;
>
> /**
> + * A register access error message
> + * @mask: Bits in the register the error applies to
> + * @reason: Reason why this access is an error
> + */
> +
> +typedef struct RegisterAccessError {
> + uint64_t mask;
> + const char *reason;
> +} RegisterAccessError;
This seems out of place here. It's not used by any of the code.
> +
> +#define REG_GPIO_POL_HIGH 0
> +#define REG_GPIO_POL_LOW 1
> +
> +typedef struct RegisterGPIOMapping {
> + const char *name;
> + uint8_t bit_pos;
> + bool input;
> + bool polarity;
> + uint8_t num;
> + uint8_t width;
> +} RegisterGPIOMapping;
> +
> +/**
> * Access description for a register that is part of guest accessible device
> * state.
> *
> @@ -61,6 +85,8 @@ struct RegisterAccessInfo {
>
> uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
>
> + const RegisterGPIOMapping *gpios;
> +
> struct {
> hwaddr addr;
> } decode;
> @@ -137,6 +163,17 @@ void register_reset(RegisterInfo *reg);
> void register_init(RegisterInfo *reg);
>
> /**
> + * Refresh GPIO outputs based on diff between old value register current value.
> + * GPIOs are refreshed for fields where the old value differs to the current
> + * value.
> + *
> + * @reg: Register to refresh GPIO outs
> + * @old_value: previous value of register
> + */
> +
> +void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value);
> +
> +/**
> * Memory API MMIO write handler that will write to a Register API register.
> * _be for big endian variant and _le for little endian.
> * @opaque: RegisterInfo to write to
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/16] data-driven device registers
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
` (15 preceding siblings ...)
2016-02-26 16:15 ` [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alex Bennée
@ 2016-02-29 12:26 ` Alex Bennée
2016-03-03 21:27 ` Alistair Francis
16 siblings, 1 reply; 35+ messages in thread
From: Alex Bennée @ 2016-02-29 12:26 UTC (permalink / raw)
To: Alistair Francis
Cc: edgar.iglesias, peter.maydell, qemu-devel, crosthwaitepeter,
edgar.iglesias, afaerber, fred.konrad
Alistair Francis <alistair.francis@xilinx.com> writes:
> This patch series is based on Peter C's original register API. His
> original cover letter is below.
>
> I have added a new function memory_region_add_subregion_no_print() which
> stops memory regions from being printed by 'info mtree'. This is used to
> avoid evey register being printed when running 'info mtree'.
OK I've finished my pass of v4. In general I think it is looking OK. I
think the main things that remain to be addressed are:
- not breaking up MemoryRegions for each individual register
- adding some access MACROs to aid reading/grepping of macro defined
registers
- some patches have un-related changes in them
Let me know when v5 is ready ;-)
>
> NOTE: That info qom-tree will still print all of these registers.
>
> Future work: Allow support for memory attributes.
>
> V4:
> - Rebase and fix build issue
> - Simplify the register write logic
> - Other small fixes suggested by Alex Bennee
> V3:
> - Small changes reported by Fred
> V2:
> - Rebase
> - Fix up IOU SLCR connections
> - Add the memory_region_add_subregion_no_print() function and use it
> for the registers
> Changes since RFC:
> - Connect the ZynqMP IOU SLCR device
> - Rebase
>
> Original cover letter From Peter:
> Hi All. This is a new scheme I've come up with handling device registers in a
> data driven way. My motivation for this is to factor out a lot of the access
> checking that seems to be replicated in every device. See P1 commit message for
> further discussion.
>
> P1 is the main patch, adds the register definition functionality
> P2-3,6 add helpers that glue the register API to the Memory API
> P4 Defines a set of macros that minimise register and field definitions
> P5 is QOMfication
> P7 is a trivial
> P10-13 Work up to GPIO support
> P8,9,14 add new devices (the Xilinx Zynq devcfg & ZynqMP SLCR) that use this
> scheme.
> P15: Connect the ZynqMP SLCR device
>
> This Zynq devcfg device was particularly finnicky with per-bit restrictions.
> I'm also looking for a higher-than-usual modelling fidelity
> on the register space, with semantics defined for random reserved bits
> in-between otherwise consistent fields.
>
> Here's an example of the qemu_log output for the devcfg device. This is produced
> by now generic sharable code:
>
> /machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508
> /machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010
> /machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value ffffffff
> /machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f
>
> And an example of a rogue guest banging on a bad bit:
>
> /machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not be \
> written to 1
>
> A future feature I am interested in is implementing TCG optimisation of
> side-effectless registers. The register API allows clear definition of
> what registers have txn side effects and which ones don't. You could even
> go a step further and translate such side-effectless accesses based on the
> data pointer for the register.
>
>
> Alistair Francis (3):
> memory: Allow subregions to not be printed by info mtree
> register: Add Register API
> xlnx-zynqmp: Connect the ZynqMP IOU SLCR
>
> Peter Crosthwaite (13):
> register: Add Memory API glue
> register: Add support for decoding information
> register: Define REG and FIELD macros
> register: QOMify
> register: Add block initialise helper
> bitops: Add ONES macro
> dma: Add Xilinx Zynq devcfg device model
> xilinx_zynq: add devcfg to machine model
> qdev: Define qdev_get_gpio_out
> qdev: Add qdev_pass_all_gpios API
> irq: Add opaque setter routine
> register: Add GPIO API
> misc: Introduce ZynqMP IOU SLCR
>
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/xilinx_zynq.c | 8 +
> hw/arm/xlnx-zynqmp.c | 13 ++
> hw/core/Makefile.objs | 1 +
> hw/core/irq.c | 5 +
> hw/core/qdev.c | 21 ++
> hw/core/register.c | 348 +++++++++++++++++++++++++++++
> hw/dma/Makefile.objs | 1 +
> hw/dma/xlnx-zynq-devcfg.c | 393 +++++++++++++++++++++++++++++++++
> hw/misc/Makefile.objs | 1 +
> hw/misc/xlnx-zynqmp-iou-slcr.c | 113 ++++++++++
> include/exec/memory.h | 17 ++
> include/hw/arm/xlnx-zynqmp.h | 2 +
> include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
> include/hw/irq.h | 2 +
> include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++
> include/hw/qdev-core.h | 3 +
> include/hw/register.h | 260 ++++++++++++++++++++++
> include/qemu/bitops.h | 2 +
> memory.c | 10 +-
> 20 files changed, 1309 insertions(+), 1 deletion(-)
> create mode 100644 hw/core/register.c
> create mode 100644 hw/dma/xlnx-zynq-devcfg.c
> create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c
> create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
> create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h
> create mode 100644 include/hw/register.h
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/16] data-driven device registers
2016-02-29 12:26 ` Alex Bennée
@ 2016-03-03 21:27 ` Alistair Francis
2016-03-08 1:21 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2016-03-03 21:27 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Alistair Francis, Peter Crosthwaite, Edgar Iglesias,
Andreas Färber, KONRAD Frédéric
On Mon, Feb 29, 2016 at 4:26 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alistair Francis <alistair.francis@xilinx.com> writes:
>
>> This patch series is based on Peter C's original register API. His
>> original cover letter is below.
>>
>> I have added a new function memory_region_add_subregion_no_print() which
>> stops memory regions from being printed by 'info mtree'. This is used to
>> avoid evey register being printed when running 'info mtree'.
>
> OK I've finished my pass of v4. In general I think it is looking OK. I
> think the main things that remain to be addressed are:
>
> - not breaking up MemoryRegions for each individual register
> - adding some access MACROs to aid reading/grepping of macro defined
> registers
> - some patches have un-related changes in them
>
> Let me know when v5 is ready ;-)
Thanks for your review, I'll go through and address your comments.
Thanks,
Alistair
>
>>
>> NOTE: That info qom-tree will still print all of these registers.
>>
>> Future work: Allow support for memory attributes.
>>
>> V4:
>> - Rebase and fix build issue
>> - Simplify the register write logic
>> - Other small fixes suggested by Alex Bennee
>> V3:
>> - Small changes reported by Fred
>> V2:
>> - Rebase
>> - Fix up IOU SLCR connections
>> - Add the memory_region_add_subregion_no_print() function and use it
>> for the registers
>> Changes since RFC:
>> - Connect the ZynqMP IOU SLCR device
>> - Rebase
>>
>> Original cover letter From Peter:
>> Hi All. This is a new scheme I've come up with handling device registers in a
>> data driven way. My motivation for this is to factor out a lot of the access
>> checking that seems to be replicated in every device. See P1 commit message for
>> further discussion.
>>
>> P1 is the main patch, adds the register definition functionality
>> P2-3,6 add helpers that glue the register API to the Memory API
>> P4 Defines a set of macros that minimise register and field definitions
>> P5 is QOMfication
>> P7 is a trivial
>> P10-13 Work up to GPIO support
>> P8,9,14 add new devices (the Xilinx Zynq devcfg & ZynqMP SLCR) that use this
>> scheme.
>> P15: Connect the ZynqMP SLCR device
>>
>> This Zynq devcfg device was particularly finnicky with per-bit restrictions.
>> I'm also looking for a higher-than-usual modelling fidelity
>> on the register space, with semantics defined for random reserved bits
>> in-between otherwise consistent fields.
>>
>> Here's an example of the qemu_log output for the devcfg device. This is produced
>> by now generic sharable code:
>>
>> /machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508
>> /machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010
>> /machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value ffffffff
>> /machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f
>>
>> And an example of a rogue guest banging on a bad bit:
>>
>> /machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not be \
>> written to 1
>>
>> A future feature I am interested in is implementing TCG optimisation of
>> side-effectless registers. The register API allows clear definition of
>> what registers have txn side effects and which ones don't. You could even
>> go a step further and translate such side-effectless accesses based on the
>> data pointer for the register.
>>
>>
>> Alistair Francis (3):
>> memory: Allow subregions to not be printed by info mtree
>> register: Add Register API
>> xlnx-zynqmp: Connect the ZynqMP IOU SLCR
>>
>> Peter Crosthwaite (13):
>> register: Add Memory API glue
>> register: Add support for decoding information
>> register: Define REG and FIELD macros
>> register: QOMify
>> register: Add block initialise helper
>> bitops: Add ONES macro
>> dma: Add Xilinx Zynq devcfg device model
>> xilinx_zynq: add devcfg to machine model
>> qdev: Define qdev_get_gpio_out
>> qdev: Add qdev_pass_all_gpios API
>> irq: Add opaque setter routine
>> register: Add GPIO API
>> misc: Introduce ZynqMP IOU SLCR
>>
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/xilinx_zynq.c | 8 +
>> hw/arm/xlnx-zynqmp.c | 13 ++
>> hw/core/Makefile.objs | 1 +
>> hw/core/irq.c | 5 +
>> hw/core/qdev.c | 21 ++
>> hw/core/register.c | 348 +++++++++++++++++++++++++++++
>> hw/dma/Makefile.objs | 1 +
>> hw/dma/xlnx-zynq-devcfg.c | 393 +++++++++++++++++++++++++++++++++
>> hw/misc/Makefile.objs | 1 +
>> hw/misc/xlnx-zynqmp-iou-slcr.c | 113 ++++++++++
>> include/exec/memory.h | 17 ++
>> include/hw/arm/xlnx-zynqmp.h | 2 +
>> include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
>> include/hw/irq.h | 2 +
>> include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++
>> include/hw/qdev-core.h | 3 +
>> include/hw/register.h | 260 ++++++++++++++++++++++
>> include/qemu/bitops.h | 2 +
>> memory.c | 10 +-
>> 20 files changed, 1309 insertions(+), 1 deletion(-)
>> create mode 100644 hw/core/register.c
>> create mode 100644 hw/dma/xlnx-zynq-devcfg.c
>> create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c
>> create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
>> create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h
>> create mode 100644 include/hw/register.h
>
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API
2016-02-29 12:22 ` Alex Bennée
@ 2016-03-04 18:47 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-04 18:47 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Alistair Francis, Peter Crosthwaite, Edgar Iglesias,
Andreas Färber, KONRAD Frédéric
On Mon, Feb 29, 2016 at 4:22 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alistair Francis <alistair.francis@xilinx.com> writes:
>
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Add GPIO functionality to the register API. This allows association
>> and automatic connection of GPIOs to bits in registers. GPIO inputs
>> will attach to handlers that automatically set read-only bits in
>> registers. GPIO outputs will be updated to reflect their field value
>> when their respective registers are written (or reset). Supports
>> active low GPIOs.
>>
>> This is particularly effective for implementing system level
>> controllers, where heterogenous collections of control signals are
>> placed is a SoC specific peripheral then propagated all over the
>> system.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> [ EI Changes:
>> * register: Add a polarity field to GPIO connections
>> Makes it possible to directly connect active low signals
>> to generic interrupt pins.
>> ]
>> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>>
>> hw/core/register.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/register.h | 37 ++++++++++++++++++++
>> 2 files changed, 133 insertions(+)
>>
>> diff --git a/hw/core/register.c b/hw/core/register.c
>> index ac866f6..1dc7ccc 100644
>> --- a/hw/core/register.c
>> +++ b/hw/core/register.c
>> @@ -106,6 +106,7 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we)
>> }
>>
>> register_write_val(reg, new_val);
>> + register_refresh_gpios(reg, old_val);
>>
>> if (ac->post_write) {
>> ac->post_write(reg, new_val);
>> @@ -147,19 +148,113 @@ void register_reset(RegisterInfo *reg)
>> g_assert(reg);
>> g_assert(reg->data);
>> g_assert(reg->access);
>> + uint64_t old_val;
>> +
>> + old_val = register_read_val(reg);
>>
>> register_write_val(reg, reg->access->reset);
>> + register_refresh_gpios(reg, old_val);
>> +}
>> +
>> +void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value)
>> +{
>> + const RegisterAccessInfo *ac;
>> + const RegisterGPIOMapping *gpio;
>> +
>> + ac = reg->access;
>> + for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
>> + int i;
>> +
>> + if (gpio->input) {
>> + continue;
>> + }
>> +
>> + for (i = 0; i < gpio->num; ++i) {
>> + uint64_t gpio_value, gpio_value_old;
>> +
>> + qemu_irq gpo = qdev_get_gpio_out_named(DEVICE(reg), gpio->name, i);
>> + gpio_value_old = extract64(old_value,
>> + gpio->bit_pos + i * gpio->width,
>> + gpio->width) ^ gpio->polarity;
>> + gpio_value = extract64(register_read_val(reg),
>> + gpio->bit_pos + i * gpio->width,
>> + gpio->width) ^ gpio->polarity;
>> + if (!(gpio_value_old ^ gpio_value)) {
>> + continue;
>> + }
>> + if (reg->debug && gpo) {
>> + qemu_log("refreshing gpio out %s to %" PRIx64 "\n",
>> + gpio->name, gpio_value);
>> + }
>> + qemu_set_irq(gpo, gpio_value);
>> + }
>> + }
>> +}
>> +
>> +typedef struct DeviceNamedGPIOHandlerOpaque {
>> + DeviceState *dev;
>> + const char *name;
>> +} DeviceNamedGPIOHandlerOpaque;
>> +
>> +static void register_gpio_handler(void *opaque, int n, int level)
>> +{
>> + DeviceNamedGPIOHandlerOpaque *gho = opaque;
>> + RegisterInfo *reg = REGISTER(gho->dev);
>> +
>> + const RegisterAccessInfo *ac;
>> + const RegisterGPIOMapping *gpio;
>> +
>> + ac = reg->access;
>> + for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
>> + if (gpio->input && !strcmp(gho->name, gpio->name)) {
>> + register_write_val(reg, deposit64(register_read_val(reg),
>> + gpio->bit_pos + n * gpio->width,
>> + gpio->width,
>> + level ^ gpio->polarity));
>> + return;
>> + }
>> + }
>> +
>> + abort();
>> }
>>
>> void register_init(RegisterInfo *reg)
>> {
>> assert(reg);
>> + const RegisterAccessInfo *ac;
>> + const RegisterGPIOMapping *gpio;
>>
>> if (!reg->data || !reg->access) {
>> return;
>> }
>>
>> object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER);
>> +
>> + ac = reg->access;
>> + for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
>> + if (!gpio->num) {
>> + ((RegisterGPIOMapping *)gpio)->num = 1;
>> + }
>> + if (!gpio->width) {
>> + ((RegisterGPIOMapping *)gpio)->width = 1;
>> + }
>> + if (gpio->input) {
>> + DeviceNamedGPIOHandlerOpaque gho = {
>> + .name = gpio->name,
>> + .dev = DEVICE(reg),
>> + };
>> + qemu_irq irq;
>> +
>> + qdev_init_gpio_in_named(DEVICE(reg), register_gpio_handler,
>> + gpio->name, gpio->num);
>> + irq = qdev_get_gpio_in_named(DEVICE(reg), gpio->name, gpio->num);
>> + qemu_irq_set_opaque(irq, g_memdup(&gho, sizeof(gho)));
>> + } else {
>> + qemu_irq *gpos = g_new0(qemu_irq, gpio->num);
>> +
>> + qdev_init_gpio_out_named(DEVICE(reg), gpos, gpio->name, gpio->num);
>> + }
>> + }
>> }
>>
>> static inline void register_write_memory(void *opaque, hwaddr addr,
>> @@ -231,6 +326,7 @@ void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
>> .opaque = owner,
>> };
>> register_init(r);
>> + qdev_pass_all_gpios(DEVICE(r), owner);
>>
>> memory_region_init_io(&r->mem, OBJECT(owner), ops, r, r->access->name,
>> sizeof(uint32_t));
>> diff --git a/include/hw/register.h b/include/hw/register.h
>> index 6ac005c..4d284a9 100644
>> --- a/include/hw/register.h
>> +++ b/include/hw/register.h
>> @@ -13,11 +13,35 @@
>>
>> #include "hw/qdev-core.h"
>> #include "exec/memory.h"
>> +#include "hw/irq.h"
>>
>> typedef struct RegisterInfo RegisterInfo;
>> typedef struct RegisterAccessInfo RegisterAccessInfo;
>>
>> /**
>> + * A register access error message
>> + * @mask: Bits in the register the error applies to
>> + * @reason: Reason why this access is an error
>> + */
>> +
>> +typedef struct RegisterAccessError {
>> + uint64_t mask;
>> + const char *reason;
>> +} RegisterAccessError;
>
> This seems out of place here. It's not used by any of the code.
Woops, it is leftover from some other code I removed. Good catch
Thanks,
Alistair
>
>> +
>> +#define REG_GPIO_POL_HIGH 0
>> +#define REG_GPIO_POL_LOW 1
>> +
>> +typedef struct RegisterGPIOMapping {
>> + const char *name;
>> + uint8_t bit_pos;
>> + bool input;
>> + bool polarity;
>> + uint8_t num;
>> + uint8_t width;
>> +} RegisterGPIOMapping;
>> +
>> +/**
>> * Access description for a register that is part of guest accessible device
>> * state.
>> *
>> @@ -61,6 +85,8 @@ struct RegisterAccessInfo {
>>
>> uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
>>
>> + const RegisterGPIOMapping *gpios;
>> +
>> struct {
>> hwaddr addr;
>> } decode;
>> @@ -137,6 +163,17 @@ void register_reset(RegisterInfo *reg);
>> void register_init(RegisterInfo *reg);
>>
>> /**
>> + * Refresh GPIO outputs based on diff between old value register current value.
>> + * GPIOs are refreshed for fields where the old value differs to the current
>> + * value.
>> + *
>> + * @reg: Register to refresh GPIO outs
>> + * @old_value: previous value of register
>> + */
>> +
>> +void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value);
>> +
>> +/**
>> * Memory API MMIO write handler that will write to a Register API register.
>> * _be for big endian variant and _le for little endian.
>> * @opaque: RegisterInfo to write to
>
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model
2016-02-29 12:20 ` Alex Bennée
@ 2016-03-04 19:41 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-04 19:41 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Alistair Francis, Peter Crosthwaite, Edgar Iglesias,
Andreas Färber, KONRAD Frédéric
On Mon, Feb 29, 2016 at 4:20 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alistair Francis <alistair.francis@xilinx.com> writes:
>
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Minimal device model for devcfg module of Zynq. DMA capabilities and
>> interrupt generation supported.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>>
>> default-configs/arm-softmmu.mak | 1 +
>> hw/dma/Makefile.objs | 1 +
>> hw/dma/xlnx-zynq-devcfg.c | 397 ++++++++++++++++++++++++++++++++++++++
>> include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
>> 4 files changed, 461 insertions(+)
>> create mode 100644 hw/dma/xlnx-zynq-devcfg.c
>> create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
>>
>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
>> index a9f82a1..d524584 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -66,6 +66,7 @@ CONFIG_PXA2XX=y
>> CONFIG_BITBANG_I2C=y
>> CONFIG_FRAMEBUFFER=y
>> CONFIG_XILINX_SPIPS=y
>> +CONFIG_ZYNQ_DEVCFG=y
>>
>> CONFIG_ARM11SCU=y
>> CONFIG_A9SCU=y
>> diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
>> index 0e65ed0..eaf0a81 100644
>> --- a/hw/dma/Makefile.objs
>> +++ b/hw/dma/Makefile.objs
>> @@ -5,6 +5,7 @@ common-obj-$(CONFIG_PL330) += pl330.o
>> common-obj-$(CONFIG_I82374) += i82374.o
>> common-obj-$(CONFIG_I8257) += i8257.o
>> common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
>> +common-obj-$(CONFIG_ZYNQ_DEVCFG) += xlnx-zynq-devcfg.o
>> common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
>> common-obj-$(CONFIG_STP2000) += sparc32_dma.o
>> common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
>> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
>> new file mode 100644
>> index 0000000..0420123
>> --- /dev/null
>> +++ b/hw/dma/xlnx-zynq-devcfg.c
>> @@ -0,0 +1,397 @@
>> +/*
>> + * QEMU model of the Xilinx Zynq Devcfg Interface
>> + *
>> + * (C) 2011 PetaLogix Pty Ltd
>> + * (C) 2014 Xilinx Inc.
>> + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/dma/xlnx-zynq-devcfg.h"
>> +#include "qemu/bitops.h"
>> +#include "sysemu/sysemu.h"
>> +#include "sysemu/dma.h"
>> +
>> +#define FREQ_HZ 900000000
>> +
>> +#define BTT_MAX 0x400
>> +
>> +#ifndef XLNX_ZYNQ_DEVCFG_ERR_DEBUG
>> +#define XLNX_ZYNQ_DEVCFG_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT(...) do { \
>> + if (XLNX_ZYNQ_DEVCFG_ERR_DEBUG) { \
>> + qemu_log("%s: ", __func__); \
>> + qemu_log(__VA_ARGS__); \
>> + } \
>> +} while (0);
>
> This can be done in one qemu_log invocation as per other patches.
Fixed.
>
>> +
>> +REG32(CTRL, 0x00)
>> + FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */
>> + FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
>> + FIELD(CTRL, PCAP_MODE, 26, 1)
>> + FIELD(CTRL, MULTIBOOT_EN, 24, 1)
>> + FIELD(CTRL, USER_MODE, 15, 1)
>> + FIELD(CTRL, PCFG_AES_FUSE, 12, 1)
>> + FIELD(CTRL, PCFG_AES_EN, 9, 3)
>> + FIELD(CTRL, SEU_EN, 8, 1)
>> + FIELD(CTRL, SEC_EN, 7, 1)
>> + FIELD(CTRL, SPNIDEN, 6, 1)
>> + FIELD(CTRL, SPIDEN, 5, 1)
>> + FIELD(CTRL, NIDEN, 4, 1)
>> + FIELD(CTRL, DBGEN, 3, 1)
>> + FIELD(CTRL, DAP_EN, 0, 3)
>> +
>> +REG32(LOCK, 0x04)
>> + #define AES_FUSE_LOCK 4
>> + #define AES_EN_LOCK 3
>> + #define SEU_LOCK 2
>> + #define SEC_LOCK 1
>> + #define DBG_LOCK 0
>> +
>> +/* mapping bits in R_LOCK to what they lock in R_CTRL */
>> +static const uint32_t lock_ctrl_map[] = {
>> + [AES_FUSE_LOCK] = R_CTRL_PCFG_AES_FUSE_MASK,
>> + [AES_EN_LOCK] = R_CTRL_PCFG_AES_EN_MASK,
>> + [SEU_LOCK] = R_CTRL_SEU_EN_MASK,
>> + [SEC_LOCK] = R_CTRL_SEC_EN_MASK,
>> + [DBG_LOCK] = R_CTRL_SPNIDEN_MASK | R_CTRL_SPIDEN_MASK |
>> + R_CTRL_NIDEN_MASK | R_CTRL_DBGEN_MASK |
>> + R_CTRL_DAP_EN_MASK,
>> +};
>> +
>> +REG32(CFG, 0x08)
>> + FIELD(CFG, RFIFO_TH, 10, 2)
>> + FIELD(CFG, WFIFO_TH, 8, 2)
>> + FIELD(CFG, RCLK_EDGE, 7, 1)
>> + FIELD(CFG, WCLK_EDGE, 6, 1)
>> + FIELD(CFG, DISABLE_SRC_INC, 5, 1)
>> + FIELD(CFG, DISABLE_DST_INC, 4, 1)
>> +#define R_CFG_RO 0xFFFFF000
>
> If this was:
>
> FIELD(CFG, RO, 12, 20)
>
> Wouldn't you get:
>
> R_CFG_RO_MASK for free?
That's a good point, although the point of the field macros is for the
individual bits in the register, which I don't think this is, which is
why it is seperate.
The macro isn't used, so I'm just going to remove it.
>
>> +#define R_CFG_RESET 0x50B
>> +
>> +REG32(INT_STS, 0x0C)
>> + FIELD(INT_STS, PSS_GTS_USR_B, 31, 1)
>> + FIELD(INT_STS, PSS_FST_CFG_B, 30, 1)
>> + FIELD(INT_STS, PSS_CFG_RESET_B, 27, 1)
>> + FIELD(INT_STS, RX_FIFO_OV, 18, 1)
>> + FIELD(INT_STS, WR_FIFO_LVL, 17, 1)
>> + FIELD(INT_STS, RD_FIFO_LVL, 16, 1)
>> + FIELD(INT_STS, DMA_CMD_ERR, 15, 1)
>> + FIELD(INT_STS, DMA_Q_OV, 14, 1)
>> + FIELD(INT_STS, DMA_DONE, 13, 1)
>> + FIELD(INT_STS, DMA_P_DONE, 12, 1)
>> + FIELD(INT_STS, P2D_LEN_ERR, 11, 1)
>> + FIELD(INT_STS, PCFG_DONE, 2, 1)
>> + #define R_INT_STS_RSVD ((0x7 << 24) | (0x1 << 19) | (0xF < 7))
>> +
>> +REG32(INT_MASK, 0x10)
>> +
>> +REG32(STATUS, 0x14)
>> + FIELD(STATUS, DMA_CMD_Q_F, 31, 1)
>> + FIELD(STATUS, DMA_CMD_Q_E, 30, 1)
>> + FIELD(STATUS, DMA_DONE_CNT, 28, 2)
>> + FIELD(STATUS, RX_FIFO_LVL, 20, 5)
>> + FIELD(STATUS, TX_FIFO_LVL, 12, 7)
>> + FIELD(STATUS, PSS_GTS_USR_B, 11, 1)
>> + FIELD(STATUS, PSS_FST_CFG_B, 10, 1)
>> + FIELD(STATUS, PSS_CFG_RESET_B, 5, 1)
>> +
>> +REG32(DMA_SRC_ADDR, 0x18)
>> +REG32(DMA_DST_ADDR, 0x1C)
>> +REG32(DMA_SRC_LEN, 0x20)
>> +REG32(DMA_DST_LEN, 0x24)
>> +REG32(ROM_SHADOW, 0x28)
>> +REG32(SW_ID, 0x30)
>> +REG32(UNLOCK, 0x34)
>> +
>> +#define R_UNLOCK_MAGIC 0x757BDF0D
>> +
>> +REG32(MCTRL, 0x80)
>> + FIELD(MCTRL, PS_VERSION, 28, 4)
>> + FIELD(MCTRL, PCFG_POR_B, 8, 1)
>> + FIELD(MCTRL, INT_PCAP_LPBK, 4, 1)
>> + FIELD(MCTRL, QEMU, 3, 1)
>> +
>> +static void xlnx_zynq_devcfg_update_ixr(XlnxZynqDevcfg *s)
>> +{
>> + qemu_set_irq(s->irq, ~s->regs[R_INT_MASK] & s->regs[R_INT_STS]);
>
> What defines R_INT_MASK? It looks as though only FIELD() definitions
> give R_reg_field_MASK defines?
This is defined by the REG32() macro. So the line with:
'REG32(INT_MASK, 0x10)' defines this
>
> This is the problem with the "auto-magic" derived names. If I grep the
> source code for R_INT_MASK I only find the use. Actually now I realise
> that INT_MASK is a register name not a field. I think we need access
> helpers to guide the user. ~s->regs[GET_REG_NUM(INT_MASK)] would prompt
> the user to search for INT_MASK to find the original definitions.
Hmm, that is a good idea, the problem I see is that the lines of code
will end up very long. Is that something that we want?
>
>> +}
>> +
>> +static void xlnx_zynq_devcfg_reset(DeviceState *dev)
>> +{
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(dev);
>> + int i;
>> +
>> + for (i = 0; i < XLNX_ZYNQ_DEVCFG_R_MAX; ++i) {
>> + register_reset(&s->regs_info[i]);
>> + }
>> +}
>> +
>> +static void xlnx_zynq_devcfg_dma_go(XlnxZynqDevcfg *s)
>> +{
>> + for (;;) {
>> + uint8_t buf[BTT_MAX];
>> + XlnxZynqDevcfgDMACmd *dmah = s->dma_cmd_fifo;
>> + uint32_t btt = BTT_MAX;
>> + bool loopback = s->regs[R_MCTRL] & R_MCTRL_INT_PCAP_LPBK_MASK;
>> +
>> + btt = MIN(btt, dmah->src_len);
>> + if (loopback) {
>> + btt = MIN(btt, dmah->dest_len);
>> + }
>> + DB_PRINT("reading %x bytes from %x\n", btt, dmah->src_addr);
>> + dma_memory_read(&address_space_memory, dmah->src_addr, buf, btt);
>> + dmah->src_len -= btt;
>> + dmah->src_addr += btt;
>> + if (loopback) {
>> + DB_PRINT("writing %x bytes from %x\n", btt, dmah->dest_addr);
>> + dma_memory_write(&address_space_memory, dmah->dest_addr, buf, btt);
>> + dmah->dest_len -= btt;
>> + dmah->dest_addr += btt;
>> + }
>> + if (!dmah->src_len && !dmah->dest_len) {
>> + DB_PRINT("dma operation finished\n");
>> + s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
>> + R_INT_STS_DMA_P_DONE_MASK;
>> + s->dma_cmd_fifo_num--;
>> + memmove(s->dma_cmd_fifo, &s->dma_cmd_fifo[1],
>> + sizeof(*s->dma_cmd_fifo) * XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN
>> + - 1);
>> + }
>> + xlnx_zynq_devcfg_update_ixr(s);
>> + if (!s->dma_cmd_fifo_num) { /* All done */
>> + return;
>> + }
>> + }
>
> I noticed this before in other patches I think. I guess it is a
> stylistic choice but certainly for a single well defined end condition
> do () while {} reads more naturally.
I prefer do whiles as well, I have converted this one to a do while.
>
>> +}
>> +
>> +static void r_ixr_post_write(RegisterInfo *reg, uint64_t val)
>> +{
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
>> +
>> + xlnx_zynq_devcfg_update_ixr(s);
>> +}
>> +
>> +static uint64_t r_ctrl_pre_write(RegisterInfo *reg, uint64_t val)
>> +{
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(lock_ctrl_map); ++i) {
>> + if (s->regs[R_LOCK] & 1 << i) {
>> + val &= ~lock_ctrl_map[i];
>> + val |= lock_ctrl_map[i] & s->regs[R_CTRL];
>> + }
>> + }
>> + return val;
>> +}
>> +
>> +static void r_ctrl_post_write(RegisterInfo *reg, uint64_t val)
>> +{
>> + uint32_t aes_en = F_EX32(val, CTRL, PCFG_AES_EN);
>> +
>> + if (aes_en != 0 && aes_en != 7) {
>> + qemu_log_mask(LOG_UNIMP, "%s: warning, aes-en bits inconsistent,"
>> + "unimplemented security reset should happen!\n",
>> + reg->prefix);
>> + }
>> +}
>> +
>> +static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
>> +{
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
>> +
>> + if (val == R_UNLOCK_MAGIC) {
>> + DB_PRINT("successful unlock\n");
>> + /* BootROM will have already done the actual unlock so no need to do
>> + * anything in successful subsequent unlock
>> + */
>> + } else { /* bad unlock attempt */
>> + qemu_log_mask(LOG_GUEST_ERROR, "%s: failed unlock\n", reg->prefix);
>> + s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK;
>> + s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK;
>> + /* core becomes inaccessible */
>> + memory_region_set_enabled(&s->iomem, false);
>> + }
>> +}
>> +
>> +static uint64_t r_lock_pre_write(RegisterInfo *reg, uint64_t val)
>> +{
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
>> +
>> + /* once bits are locked they stay locked */
>> + return s->regs[R_LOCK] | val;
>> +}
>> +
>> +static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val)
>> +{
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
>> +
>> + s->dma_cmd_fifo[s->dma_cmd_fifo_num] = (XlnxZynqDevcfgDMACmd) {
>> + .src_addr = s->regs[R_DMA_SRC_ADDR] & ~0x3UL,
>> + .dest_addr = s->regs[R_DMA_DST_ADDR] & ~0x3UL,
>> + .src_len = s->regs[R_DMA_SRC_LEN] << 2,
>> + .dest_len = s->regs[R_DMA_DST_LEN] << 2,
>> + };
>> + s->dma_cmd_fifo_num++;
>> + DB_PRINT("dma transfer started; %d total transfers pending\n",
>> + s->dma_cmd_fifo_num);
>> + xlnx_zynq_devcfg_dma_go(s);
>> +}
>> +
>> +static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
>> + { .name = "CTRL", .decode.addr = A_CTRL,
>> + .reset = R_CTRL_PCAP_PR_MASK | R_CTRL_PCAP_MODE_MASK | 0x3 << 13,
>> + .rsvd = 0x1 << 28 | 0x3ff << 13 | 0x3 << 13,
>> + .pre_write = r_ctrl_pre_write,
>> + .post_write = r_ctrl_post_write,
>> + },
>> + { .name = "LOCK", .decode.addr = A_LOCK,
>
> The same comment can be mode for the automagic addresses.
> GET_REG_ADDR(LOCK) would be clearer.
>
>> + .rsvd = ~ONES(5),
>> + .pre_write = r_lock_pre_write,
>> + },
>> + { .name = "CFG", .decode.addr = A_CFG,
>> + .reset = 1 << R_CFG_RFIFO_TH_SHIFT | 1 << R_CFG_WFIFO_TH_SHIFT | 0x8,
>> + .rsvd = 0xfffff00f,
>> + },
>> + { .name = "INT_STS", .decode.addr = A_INT_STS,
>> + .w1c = ~R_INT_STS_RSVD,
>> + .reset = R_INT_STS_PSS_GTS_USR_B_MASK |
>> + R_INT_STS_PSS_CFG_RESET_B_MASK |
>> + R_INT_STS_WR_FIFO_LVL_MASK,
>> + .rsvd = R_INT_STS_RSVD,
>> + .post_write = r_ixr_post_write,
>> + },
>> + { .name = "INT_MASK", .decode.addr = A_INT_MASK,
>> + .reset = ~0,
>> + .rsvd = R_INT_STS_RSVD,
>> + .post_write = r_ixr_post_write,
>> + },
>> + { .name = "STATUS", .decode.addr = A_STATUS,
>> + .reset = R_STATUS_DMA_CMD_Q_E_MASK |
>> + R_STATUS_PSS_GTS_USR_B_MASK |
>> + R_STATUS_PSS_CFG_RESET_B_MASK,
>> + .ro = ~0,
>> + },
>> + { .name = "DMA_SRC_ADDR", .decode.addr = A_DMA_SRC_ADDR, },
>> + { .name = "DMA_DST_ADDR", .decode.addr = A_DMA_DST_ADDR, },
>> + { .name = "DMA_SRC_LEN", .decode.addr = A_DMA_SRC_LEN,
>> + .ro = ~ONES(27) },
>> + { .name = "DMA_DST_LEN", .decode.addr = A_DMA_DST_LEN,
>> + .ro = ~ONES(27),
>> + .post_write = r_dma_dst_len_post_write,
>> + },
>> + { .name = "ROM_SHADOW", .decode.addr = A_ROM_SHADOW,
>> + .rsvd = ~0ull,
>> + },
>> + { .name = "SW_ID", .decode.addr = A_SW_ID, },
>> + { .name = "UNLOCK", .decode.addr = A_UNLOCK,
>> + .post_write = r_unlock_post_write,
>> + },
>> + { .name = "MCTRL", .decode.addr = R_MCTRL * 4,
>> + /* Silicon 3.0 for version field, the mysterious reserved bit 23
>> + * and QEMU platform identifier.
>> + */
>> + .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU_MASK,
>> + .ro = ~R_MCTRL_INT_PCAP_LPBK_MASK,
>> + .rsvd = 0x00f00303,
>> + },
>> +};
>> +
>> +static const MemoryRegionOps xlnx_zynq_devcfg_reg_ops = {
>> + .read = register_read_memory_le,
>> + .write = register_write_memory_le,
>> + .endianness = DEVICE_LITTLE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4,
>> + }
>> +};
>> +
>> +static const VMStateDescription vmstate_xlnx_zynq_devcfg_dma_cmd = {
>> + .name = "xlnx_zynq_devcfg_dma_cmd",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32(src_addr, XlnxZynqDevcfgDMACmd),
>> + VMSTATE_UINT32(dest_addr, XlnxZynqDevcfgDMACmd),
>> + VMSTATE_UINT32(src_len, XlnxZynqDevcfgDMACmd),
>> + VMSTATE_UINT32(dest_len, XlnxZynqDevcfgDMACmd),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static const VMStateDescription vmstate_xlnx_zynq_devcfg = {
>> + .name = "xlnx_zynq_devcfg",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_STRUCT_ARRAY(dma_cmd_fifo, XlnxZynqDevcfg,
>> + XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN, 0,
>> + vmstate_xlnx_zynq_devcfg_dma_cmd,
>> + XlnxZynqDevcfgDMACmd),
>> + VMSTATE_UINT8(dma_cmd_fifo_num, XlnxZynqDevcfg),
>> + VMSTATE_UINT32_ARRAY(regs, XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG_R_MAX),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static void xlnx_zynq_devcfg_init(Object *obj)
>> +{
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(obj);
>> +
>> + sysbus_init_irq(sbd, &s->irq);
>> +
>> + memory_region_init(&s->iomem, obj, "devcfg", XLNX_ZYNQ_DEVCFG_R_MAX * 4);
>> + register_init_block32(DEVICE(obj), xlnx_zynq_devcfg_regs_info,
>> + ARRAY_SIZE(xlnx_zynq_devcfg_regs_info),
>> + s->regs_info, s->regs, &s->iomem,
>> + &xlnx_zynq_devcfg_reg_ops,
>> + XLNX_ZYNQ_DEVCFG_ERR_DEBUG);
>> + sysbus_init_mmio(sbd, &s->iomem);
>> +}
>> +
>> +static void xlnx_zynq_devcfg_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->reset = xlnx_zynq_devcfg_reset;
>> + dc->vmsd = &vmstate_xlnx_zynq_devcfg;
>> +}
>> +
>> +static const TypeInfo xlnx_zynq_devcfg_info = {
>> + .name = TYPE_XLNX_ZYNQ_DEVCFG,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(XlnxZynqDevcfg),
>> + .instance_init = xlnx_zynq_devcfg_init,
>> + .class_init = xlnx_zynq_devcfg_class_init,
>> +};
>> +
>> +static void xlnx_zynq_devcfg_register_types(void)
>> +{
>> + type_register_static(&xlnx_zynq_devcfg_info);
>> +}
>> +
>> +type_init(xlnx_zynq_devcfg_register_types)
>> diff --git a/include/hw/dma/xlnx-zynq-devcfg.h b/include/hw/dma/xlnx-zynq-devcfg.h
>> new file mode 100644
>> index 0000000..d40e5c8
>> --- /dev/null
>> +++ b/include/hw/dma/xlnx-zynq-devcfg.h
>> @@ -0,0 +1,62 @@
>> +/*
>> + * QEMU model of the Xilinx Devcfg Interface
>> + *
>> + * (C) 2011 PetaLogix Pty Ltd
>> + * (C) 2014 Xilinx Inc.
>> + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef XLNX_ZYNQ_DEVCFG_H
>> +
>> +#include "hw/register.h"
>> +#include "hw/sysbus.h"
>> +
>> +#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
>> +
>> +#define XLNX_ZYNQ_DEVCFG(obj) \
>> + OBJECT_CHECK(XlnxZynqDevcfg, (obj), TYPE_XLNX_ZYNQ_DEVCFG)
>> +
>> +#define XLNX_ZYNQ_DEVCFG_R_MAX 0x118
>> +
>> +#define XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN 10
>> +
>> +typedef struct XlnxZynqDevcfgDMACmd {
>> + uint32_t src_addr;
>> + uint32_t dest_addr;
>> + uint32_t src_len;
>> + uint32_t dest_len;
>> +} XlnxZynqDevcfgDMACmd;
>> +
>> +typedef struct XlnxZynqDevcfg {
>> + SysBusDevice parent_obj;
>> +
>> + MemoryRegion iomem;
>> + qemu_irq irq;
>> +
>> + XlnxZynqDevcfgDMACmd dma_cmd_fifo[XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN];
>> + uint8_t dma_cmd_fifo_num;
>> +
>> + uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
>> + RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
>> +} XlnxZynqDevcfg;
>> +
>> +#define XLNX_ZYNQ_DEVCFG_H
>> +#endif
>
>
> Sp having looked through the macro magic I'm happier with what it is
> doing. Using accessors will help with the navigation though. The common
> question someone looking over the code will want to answer is where is X
> defined.
I see what you mean, I am just a little worreid that it will result in
very long lines and it will be difficult to read.
What about just replacing A_ with A() and R_ with R()? Would that work for you?
Thanks,
Alistair
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro
2016-02-29 11:51 ` Alex Bennée
@ 2016-03-04 22:42 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-04 22:42 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Alistair Francis, Peter Crosthwaite, Edgar Iglesias,
Andreas Färber, KONRAD Frédéric
On Mon, Feb 29, 2016 at 3:51 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alistair Francis <alistair.francis@xilinx.com> writes:
>
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Little macro that just gives you N ones (justified to LSB).
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>>
>> include/qemu/bitops.h | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
>> index 8164225..27bf98d 100644
>> --- a/include/qemu/bitops.h
>> +++ b/include/qemu/bitops.h
>> @@ -430,4 +430,6 @@ static inline uint64_t deposit64(uint64_t value, int start, int length,
>> return (value & ~mask) | ((fieldval << start) & mask);
>> }
>>
>> +#define ONES(num) ((num) == 64 ? ~0ull : (1ull << (num)) - 1)
>> +
>
> I'm a little ambivalent about this one. The definition should probably
> be up at the top of the file with the other #defines. I don't like the
> name as it is a little too generic. I also notice in all the actual uses
> you immediately invert the result because you want to mask the top bits.
>
> I suspect what's needed here is a more generic helper:
>
> #define MAKE_64BIT_MASK (shift, length) \
> ...
>
> And then the:
>
> .ro = ~ONES(27) },
>
> Becomes:
>
> .ro = MAKE_64BIT_MASK(27, 64 - 27);
>
>
>> #endif
I like that idea. I have updated the implementation to use this style
instead of the ONES() style.
Thanks,
Alistair
>
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper
2016-02-29 11:28 ` Alex Bennée
@ 2016-03-08 0:09 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-08 0:09 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Alistair Francis, Peter Crosthwaite, Edgar Iglesias,
Andreas Färber, KONRAD Frédéric
On Mon, Feb 29, 2016 at 3:28 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alistair Francis <alistair.francis@xilinx.com> writes:
>
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Add a helper that will scan a static RegisterAccessInfo Array
>> and populate a container MemoryRegion with registers as defined.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> V3:
>> - Fix typo
>> V2:
>> - Use memory_region_add_subregion_no_print()
>>
>> hw/core/register.c | 29 +++++++++++++++++++++++++++++
>> include/hw/register.h | 20 ++++++++++++++++++++
>> 2 files changed, 49 insertions(+)
>>
>> diff --git a/hw/core/register.c b/hw/core/register.c
>> index d766517..ac866f6 100644
>> --- a/hw/core/register.c
>> +++ b/hw/core/register.c
>> @@ -210,6 +210,35 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size)
>> return register_read_memory(opaque, addr, size, false);
>> }
>>
>> +void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
>> + int num, RegisterInfo *ri, uint32_t *data,
>> + MemoryRegion *container, const MemoryRegionOps *ops,
>> + bool debug_enabled)
>> +{
>> + const char *debug_prefix = object_get_typename(OBJECT(owner));
>> + int i;
>> +
>> + for (i = 0; i < num; i++) {
>> + int index = rae[i].decode.addr / 4;
>> + RegisterInfo *r = &ri[index];
>> +
>> + *r = (RegisterInfo) {
>> + .data = &data[index],
>> + .data_size = sizeof(uint32_t),
>> + .access = &rae[i],
>> + .debug = debug_enabled,
>> + .prefix = debug_prefix,
>> + .opaque = owner,
>> + };
>> + register_init(r);
>> +
>> + memory_region_init_io(&r->mem, OBJECT(owner), ops, r, r->access->name,
>> + sizeof(uint32_t));
>> + memory_region_add_subregion_no_print(container,
>> + r->access->decode.addr,
>> &r->mem);
>
> As I mentioned in the previous patch I think having a subregion
> per-register is excessive. I think you need single io region with the
> private data giving a structure with the list of registers in the block.
> You can then have a general purpose set of register ops to lookup the
> eventual register and dispatch to the handler.
Ok, I figured out a pretty straightforward way to do that. Keep an eye
out for the next version.
Thanks,
Alistair
>
>> + }
>> +}
>> +
>> static const TypeInfo register_info = {
>> .name = TYPE_REGISTER,
>> .parent = TYPE_DEVICE,
>> diff --git a/include/hw/register.h b/include/hw/register.h
>> index d3469c6..6ac005c 100644
>> --- a/include/hw/register.h
>> +++ b/include/hw/register.h
>> @@ -162,6 +162,26 @@ void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
>> uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size);
>> uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size);
>>
>> +/**
>> + * Init a block of consecutive registers into a container MemoryRegion. A
>> + * number of constant register definitions are parsed to create a corresponding
>> + * array of RegisterInfo's.
>> + *
>> + * @owner: device owning the registers
>> + * @rae: Register definitions to init
>> + * @num: number of registers to init (length of @rae)
>> + * @ri: Register array to init
>> + * @data: Array to use for register data
>> + * @container: Memory region to contain new registers
>> + * @ops: Memory region ops to access registers.
>> + * @debug enabled: turn on/off verbose debug information
>> + */
>> +
>> +void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae,
>> + int num, RegisterInfo *ri, uint32_t *data,
>> + MemoryRegion *container, const MemoryRegionOps *ops,
>> + bool debug_enabled);
>> +
>> /* Define constants for a 32 bit register */
>> #define REG32(reg, addr) \
>> enum { A_ ## reg = (addr) }; \
>
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree
2016-02-26 16:54 ` Peter Maydell
@ 2016-03-08 0:49 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-08 0:49 UTC (permalink / raw)
To: Peter Maydell
Cc: Edgar Iglesias, QEMU Developers, Alistair Francis,
Peter Crosthwaite, Edgar E. Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Fri, Feb 26, 2016 at 8:54 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 26 February 2016 at 16:51, Alex Bennée <alex.bennee@linaro.org> wrote:
>> I think this needlessly complicates the memory region code and I'm not
>> sure what is too be gained for the register code. The only usage of the
>> code is inside a loop in register_init_block32. In each case the region
>> has the same set of ops. Why isn't a single region being created with an
>> indirect handler which can dispatch to the individual register handling
>> code?
>>
>> While its true some drivers create individual IO regions by an large
>> most are creating a block with a common handler.
>
> Yeah, I have to say I'm not really convinced about having one MR
> per register -- the MR code was never intended to be used that way,
> and it seems like a good way to find nasty performance or memory
> usage surprises.
I have removed the one memory region per register.
Thanks,
Alistair
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 02/16] register: Add Register API
2016-02-26 17:13 ` Alex Bennée
@ 2016-03-08 0:54 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-08 0:54 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Alistair Francis, Peter Crosthwaite, Edgar Iglesias,
Andreas Färber, KONRAD Frédéric
On Fri, Feb 26, 2016 at 9:13 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alistair Francis <alistair.francis@xilinx.com> writes:
>
>> This API provides some encapsulation of registers and factors our some
>> common functionality to common code. Bits of device state (usually MMIO
>> registers), often have all sorts of access restrictions and semantics
>> associated with them. This API allow you to define what those
>> restrictions are on a bit-by-bit basis.
>>
>> Helper functions are then used to access the register which observe the
>> semantics defined by the RegisterAccessInfo struct.
>>
>> Some features:
>> Bits can be marked as read_only (ro field)
>> Bits can be marked as write-1-clear (w1c field)
>> Bits can be marked as reserved (rsvd field)
>> Reset values can be defined (reset)
>> Bits can throw guest errors when written certain values (ge0, ge1)
>> Bits can throw unimp errors when written certain values (ui0, ui1)
>> Bits can be marked clear on read (cor)
>> Pre and post action callbacks can be added to read and write ops
>> Verbose debugging info can be enabled/disabled
>>
>> Useful for defining device register spaces in a data driven way. Cuts
>> down on a lot of the verbosity and repetition in the switch-case blocks
>> in the standard foo_mmio_read/write functions.
>>
>> Also useful for automated generation of device models from hardware
>> design sources.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> V4:
>> - Rebase
>> - Remove the guest error masking
>> - Simplify the unimplemented masking
>> - Use the reserved value in the write calculations
>> - Remove read_lite and write_lite
>> - General fixes to asserts and log printing
>> V3:
>> - Address some comments from Fred
>>
>> hw/core/Makefile.objs | 1 +
>> hw/core/register.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/register.h | 111 ++++++++++++++++++++++++++++++++++++
>> 3 files changed, 264 insertions(+)
>> create mode 100644 hw/core/register.c
>> create mode 100644 include/hw/register.h
>>
>> diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
>> index abb3560..bf95db5 100644
>> --- a/hw/core/Makefile.objs
>> +++ b/hw/core/Makefile.objs
>> @@ -14,4 +14,5 @@ common-obj-$(CONFIG_SOFTMMU) += machine.o
>> common-obj-$(CONFIG_SOFTMMU) += null-machine.o
>> common-obj-$(CONFIG_SOFTMMU) += loader.o
>> common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
>> +common-obj-$(CONFIG_SOFTMMU) += register.o
>> common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o
>> diff --git a/hw/core/register.c b/hw/core/register.c
>> new file mode 100644
>> index 0000000..7e47df5
>> --- /dev/null
>> +++ b/hw/core/register.c
>> @@ -0,0 +1,152 @@
>> +/*
>> + * Register Definition API
>> + *
>> + * Copyright (c) 2013 Xilinx Inc.
>> + * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2. See
>> + * the COPYING file in the top-level directory.
>> + */
>> +
>> +#include "hw/register.h"
>> +#include "hw/qdev.h"
>> +#include "qemu/log.h"
>> +
>> +static inline void register_write_log(int mask, RegisterInfo *reg, int dir,
>> + uint64_t val, const char *msg,
>> + const char *reason)
>> +{
>> + qemu_log_mask(mask, "%s:%s bits %#" PRIx64 " %s write of %d%s%s\n",
>> + reg->prefix, reg->access->name, val, msg, dir,
>> + reason ? ": " : "", reason ? reason : "");
>> +}
>
> This seems unused, I guess the compiler ignores unused inlines through :-/
Good catch, removed.
>
>> +
>> +static inline void register_write_val(RegisterInfo *reg, uint64_t val)
>> +{
>> + g_assert(reg->data);
>> +
>> + switch (reg->data_size) {
>> + case 1:
>> + *(uint8_t *)reg->data = val;
>> + break;
>> + case 2:
>> + *(uint16_t *)reg->data = val;
>> + break;
>> + case 4:
>> + *(uint32_t *)reg->data = val;
>> + break;
>> + case 8:
>> + *(uint64_t *)reg->data = val;
>> + break;
>> + default:
>> + g_assert_not_reached();
>> + }
>> +}
>> +
>> +static inline uint64_t register_read_val(RegisterInfo *reg)
>> +{
>> + switch (reg->data_size) {
>> + case 1:
>> + return *(uint8_t *)reg->data;
>> + case 2:
>> + return *(uint16_t *)reg->data;
>> + case 4:
>> + return *(uint32_t *)reg->data;
>> + case 8:
>> + return *(uint64_t *)reg->data;
>> + default:
>> + g_assert_not_reached();
>> + }
>> + return 0; /* unreachable */
>> +}
>> +
>> +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we)
>> +{
>> + uint64_t old_val, new_val, test, no_w_mask;
>> + const RegisterAccessInfo *ac;
>> +
>> + assert(reg);
>> +
>> + ac = reg->access;
>> +
>> + if (!ac || !ac->name) {
>> + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
>> + "(written value: %#" PRIx64 ")\n", reg->prefix, val);
>> + return;
>> + }
>> +
>> + old_val = reg->data ? register_read_val(reg) : ac->reset;
>> +
>> + test = (old_val ^ val) & ac->rsvd;
>> + if (test) {
>> + qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit"
>> + "fields: %#" PRIx64 ")\n", reg->prefix, test);
>> + }
>> +
>> + test = val & ac->unimp;
>> + if (test) {
>> + qemu_log_mask(LOG_UNIMP,
>> + "%s:%s writing %#" PRIx64 " to unimplemented bits:" \
>> + " %#" PRIx64 "",
>> + reg->prefix, reg->access->name, val, ac->unimp);
>> + }
>> +
>> +
>> + no_w_mask = ac->ro | ac->w1c | ac->rsvd | ~we;
>> + new_val = (val & ~no_w_mask) | (old_val & no_w_mask);
>> + new_val &= ~(val & ac->w1c);
>
> A comment wouldn't go amiss here describing the concatenation of
> restrictions, RAZ, and ROW bits.
Agreed, I have added a comment.
>
>> +
>> + if (ac->pre_write) {
>> + new_val = ac->pre_write(reg, new_val);
>> + }
>> +
>> + if (reg->debug) {
>> + qemu_log("%s:%s: write of value %#" PRIx64 "\n", reg->prefix, ac->name,
>> + new_val);
>> + }
>> +
>> + register_write_val(reg, new_val);
>> +
>> + if (ac->post_write) {
>> + ac->post_write(reg, new_val);
>> + }
>> +}
>> +
>> +uint64_t register_read(RegisterInfo *reg)
>> +{
>> + uint64_t ret;
>> + const RegisterAccessInfo *ac;
>> +
>> + assert(reg);
>> +
>> + ac = reg->access;
>> + if (!ac || !ac->name) {
>> + qemu_log_mask(LOG_GUEST_ERROR, "%s: read from undefined device state\n",
>> + reg->prefix);
>> + return 0;
>> + }
>> +
>> + ret = reg->data ? register_read_val(reg) : ac->reset;
>> +
>> + register_write_val(reg, ret & ~ac->cor);
>> +
>> + if (ac->post_read) {
>> + ret = ac->post_read(reg, ret);
>> + }
>> +
>> + if (reg->debug) {
>> + qemu_log("%s:%s: read of value %#" PRIx64 "\n", reg->prefix,
>> + ac->name, ret);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +void register_reset(RegisterInfo *reg)
>> +{
>> + g_assert(reg);
>> + g_assert(reg->data);
>> + g_assert(reg->access);
>> +
>> + register_write_val(reg, reg->access->reset);
>> +}
>> diff --git a/include/hw/register.h b/include/hw/register.h
>> new file mode 100644
>> index 0000000..444239c
>> --- /dev/null
>> +++ b/include/hw/register.h
>> @@ -0,0 +1,111 @@
>> +/*
>> + * Register Definition API
>> + *
>> + * Copyright (c) 2013 Xilinx Inc.
>> + * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2. See
>> + * the COPYING file in the top-level directory.
>> + */
>> +
>> +#ifndef REGISTER_H
>> +#define REGISTER_H
>> +
>> +#include "exec/memory.h"
>> +
>> +typedef struct RegisterInfo RegisterInfo;
>> +typedef struct RegisterAccessInfo RegisterAccessInfo;
>> +
>> +/**
>> + * Access description for a register that is part of guest accessible device
>> + * state.
>> + *
>> + * @name: String name of the register
>> + * @ro: whether or not the bit is read-only
>> + * @w1c: bits with the common write 1 to clear semantic.
>> + * @reset: reset value.
>> + * @cor: Bits that are clear on read
>> + * @rsvd: Bits that are reserved and should not be changed
>> + *
>> + * @ui1: Bits that when written 1 indicate use of an unimplemented feature
>> + * @ui0: Bits that when written 0 indicate use of an unimplemented
>> feature
>
> Last two comments don't match actual definition.
Yep, they were left over. Removed.
Thanks,
Alistair
>
>> + *
>> + * @pre_write: Pre write callback. Passed the value that's to be written,
>> + * immediately before the actual write. The returned value is what is written,
>> + * giving the handler a chance to modify the written value.
>> + * @post_write: Post write callback. Passed the written value. Most write side
>> + * effects should be implemented here.
>> + *
>> + * @post_read: Post read callback. Passes the value that is about to be returned
>> + * for a read. The return value from this function is what is ultimately read,
>> + * allowing this function to modify the value before return to the client.
>> + */
>> +
>> +struct RegisterAccessInfo {
>> + const char *name;
>> + uint64_t ro;
>> + uint64_t w1c;
>> + uint64_t reset;
>> + uint64_t cor;
>> + uint64_t rsvd;
>> + uint64_t unimp;
>> +
>> + uint64_t (*pre_write)(RegisterInfo *reg, uint64_t val);
>> + void (*post_write)(RegisterInfo *reg, uint64_t val);
>> +
>> + uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
>> +};
>> +
>> +/**
>> + * A register that is part of guest accessible state
>> + * @data: pointer to the register data. Will be cast
>> + * to the relevant uint type depending on data_size.
>> + * @data_size: Size of the register in bytes. Must be
>> + * 1, 2, 4 or 8
>> + *
>> + * @access: Access description of this register
>> + *
>> + * @debug: Whether or not verbose debug is enabled
>> + * @prefix: String prefix for log and debug messages
>> + *
>> + * @opaque: Opaque data for the register
>> + */
>> +
>> +struct RegisterInfo {
>> + /* <public> */
>> + void *data;
>> + int data_size;
>> +
>> + const RegisterAccessInfo *access;
>> +
>> + bool debug;
>> + const char *prefix;
>> +
>> + void *opaque;
>> +};
>> +
>> +/**
>> + * write a value to a register, subject to its restrictions
>> + * @reg: register to write to
>> + * @val: value to write
>> + * @we: write enable mask
>> + */
>> +
>> +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we);
>> +
>> +/**
>> + * read a value from a register, subject to its restrictions
>> + * @reg: register to read from
>> + * returns: value read
>> + */
>> +
>> +uint64_t register_read(RegisterInfo *reg);
>> +
>> +/**
>> + * reset a register
>> + * @reg: register to reset
>> + */
>> +
>> +void register_reset(RegisterInfo *reg);
>> +
>> +#endif
>
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 03/16] register: Add Memory API glue
2016-02-26 17:25 ` Alex Bennée
@ 2016-03-08 1:18 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-08 1:18 UTC (permalink / raw)
To: Alex Bennée
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Alistair Francis, Peter Crosthwaite, Edgar Iglesias,
Andreas Färber, KONRAD Frédéric
On Fri, Feb 26, 2016 at 9:25 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Alistair Francis <alistair.francis@xilinx.com> writes:
>
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Add memory io handlers that glue the register API to the memory API.
>> Just translation functions at this stage. Although it does allow for
>> devices to be created without all-in-one mmio r/w handlers.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>>
>> hw/core/register.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/register.h | 31 +++++++++++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>>
>> diff --git a/hw/core/register.c b/hw/core/register.c
>> index 7e47df5..9cd50c8 100644
>> --- a/hw/core/register.c
>> +++ b/hw/core/register.c
>> @@ -150,3 +150,51 @@ void register_reset(RegisterInfo *reg)
>>
>> register_write_val(reg, reg->access->reset);
>> }
>> +
>> +static inline void register_write_memory(void *opaque, hwaddr addr,
>> + uint64_t value, unsigned size, bool be)
>> +{
>> + RegisterInfo *reg = opaque;
>> + uint64_t we = ~0;
>> + int shift = 0;
>> +
>> + if (reg->data_size != size) {
>> + we = (size == 8) ? ~0ull : (1ull << size * 8) - 1;
>> + shift = 8 * (be ? reg->data_size - size - addr : addr);
>> + }
>
> What happens if the user writes too large a value at once to the
> register? I haven't attempted to decode the shift magic going on here
> but perhaps the handling would be clearer if there was a:
>
> if (size > reg->data_size) {
> ..deal with it..
> } else if (size < data_size ) {
> ..do other magic..
> }
Good point. I think I have tidied this up.
>
>> +
>> + assert(size + addr <= reg->data_size);
>
> Why are we asserting expected input conditions after we've done stuff?
I am not sure why this is here. Removed.
>
>> + register_write(reg, value << shift, we << shift);
>> +}
>> +
>> +void register_write_memory_be(void *opaque, hwaddr addr, uint64_t value,
>> + unsigned size)
>> +{
>> + register_write_memory(opaque, addr, value, size, true);
>> +}
>> +
>> +
>> +void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
>> + unsigned size)
>> +{
>> + register_write_memory(opaque, addr, value, size, false);
>> +}
>> +
>> +static inline uint64_t register_read_memory(void *opaque, hwaddr addr,
>> + unsigned size, bool be)
>> +{
>> + RegisterInfo *reg = opaque;
>> + int shift = 8 * (be ? reg->data_size - size - addr : addr);
>> +
>
> Well we never have to deal with an over/undersized read? I suspect the
> magic above might not correctly represent some hardware when presented
> with such a thing on the bus.
I think I have fixed this up.
>
>> + return register_read(reg) >> shift;
>> +}
>> +
>> +uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size)
>> +{
>> + return register_read_memory(opaque, addr, size, true);
>> +}
>> +
>> +uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size)
>> +{
>> + return register_read_memory(opaque, addr, size, false);
>> +}
>> diff --git a/include/hw/register.h b/include/hw/register.h
>> index 444239c..9aa9cfc 100644
>> --- a/include/hw/register.h
>> +++ b/include/hw/register.h
>> @@ -69,9 +69,14 @@ struct RegisterAccessInfo {
>> * @prefix: String prefix for log and debug messages
>> *
>> * @opaque: Opaque data for the register
>> + *
>> + * @mem: optional Memory region for the register
>> */
>>
>> struct RegisterInfo {
>> + /* <private> */
>> + MemoryRegion mem;
>> +
>
> This seems unconnected with adding the helpers. Should it come with the
> original definition or when it actually gets used?
I think it should be added in this patch (although in the next version
it is added in a different struct) as this is starting to add the
memory infrastructure.
Thanks,
Alistair
>
>> /* <public> */
>> void *data;
>> int data_size;
>> @@ -108,4 +113,30 @@ uint64_t register_read(RegisterInfo *reg);
>>
>> void register_reset(RegisterInfo *reg);
>>
>> +/**
>> + * Memory API MMIO write handler that will write to a Register API register.
>> + * _be for big endian variant and _le for little endian.
>> + * @opaque: RegisterInfo to write to
>> + * @addr: Address to write
>> + * @value: Value to write
>> + * @size: Number of bytes to write
>> + */
>> +
>> +void register_write_memory_be(void *opaque, hwaddr addr, uint64_t value,
>> + unsigned size);
>> +void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value,
>> + unsigned size);
>> +
>> +/**
>> + * Memory API MMIO read handler that will read from a Register API register.
>> + * _be for big endian variant and _le for little endian.
>> + * @opaque: RegisterInfo to read from
>> + * @addr: Address to read
>> + * @size: Number of bytes to read
>> + * returns: Value read from register
>> + */
>> +
>> +uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size);
>> +uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size);
>> +
>> #endif
>
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/16] data-driven device registers
2016-03-03 21:27 ` Alistair Francis
@ 2016-03-08 1:21 ` Alistair Francis
0 siblings, 0 replies; 35+ messages in thread
From: Alistair Francis @ 2016-03-08 1:21 UTC (permalink / raw)
To: Alistair Francis
Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers,
Peter Crosthwaite, Edgar Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Thu, Mar 3, 2016 at 1:27 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Mon, Feb 29, 2016 at 4:26 AM, Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>> Alistair Francis <alistair.francis@xilinx.com> writes:
>>
>>> This patch series is based on Peter C's original register API. His
>>> original cover letter is below.
>>>
>>> I have added a new function memory_region_add_subregion_no_print() which
>>> stops memory regions from being printed by 'info mtree'. This is used to
>>> avoid evey register being printed when running 'info mtree'.
>>
>> OK I've finished my pass of v4. In general I think it is looking OK. I
>> think the main things that remain to be addressed are:
>>
>> - not breaking up MemoryRegions for each individual register
>> - adding some access MACROs to aid reading/grepping of macro defined
>> registers
>> - some patches have un-related changes in them
>>
>> Let me know when v5 is ready ;-)
>
> Thanks for your review, I'll go through and address your comments.
>
I have made some large changes to the API infrastructure so now only a
single memory region is created.
The individual registers still have all of the control (instead of
moving it to a central area) as I think it allows more customisations
in the future if required.
Thanks,
Alistair
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2016-03-08 1:21 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-09 22:14 [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 01/16] memory: Allow subregions to not be printed by info mtree Alistair Francis
2016-02-26 16:51 ` Alex Bennée
2016-02-26 16:54 ` Peter Maydell
2016-03-08 0:49 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 02/16] register: Add Register API Alistair Francis
2016-02-26 17:13 ` Alex Bennée
2016-03-08 0:54 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 03/16] register: Add Memory API glue Alistair Francis
2016-02-26 17:25 ` Alex Bennée
2016-03-08 1:18 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 04/16] register: Add support for decoding information Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 05/16] register: Define REG and FIELD macros Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 06/16] register: QOMify Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper Alistair Francis
2016-02-29 11:28 ` Alex Bennée
2016-03-08 0:09 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 08/16] bitops: Add ONES macro Alistair Francis
2016-02-29 11:51 ` Alex Bennée
2016-03-04 22:42 ` Alistair Francis
2016-02-09 22:14 ` [Qemu-devel] [PATCH v4 09/16] dma: Add Xilinx Zynq devcfg device model Alistair Francis
2016-02-29 12:20 ` Alex Bennée
2016-03-04 19:41 ` Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 11/16] qdev: Define qdev_get_gpio_out Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 12/16] qdev: Add qdev_pass_all_gpios API Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 13/16] irq: Add opaque setter routine Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 14/16] register: Add GPIO API Alistair Francis
2016-02-29 12:22 ` Alex Bennée
2016-03-04 18:47 ` Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 15/16] misc: Introduce ZynqMP IOU SLCR Alistair Francis
2016-02-09 22:15 ` [Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the " Alistair Francis
2016-02-26 16:15 ` [Qemu-devel] [PATCH v4 00/16] data-driven device registers Alex Bennée
2016-02-29 12:26 ` Alex Bennée
2016-03-03 21:27 ` Alistair Francis
2016-03-08 1:21 ` Alistair Francis
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