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From: Jagannathan Raman <jag.raman@oracle.com>
To: qemu-devel@nongnu.org
Cc: elena.ufimtseva@oracle.com, fam@euphon.net,
	swapnil.ingle@nutanix.com, john.g.johnson@oracle.com,
	kraxel@redhat.com, jag.raman@oracle.com, quintela@redhat.com,
	mst@redhat.com, armbru@redhat.com, kanth.ghatraju@oracle.com,
	felipe@nutanix.com, thuth@redhat.com, ehabkost@redhat.com,
	konrad.wilk@oracle.com, dgilbert@redhat.com,
	alex.williamson@redhat.com, stefanha@redhat.com,
	thanos.makatos@nutanix.com, rth@twiddle.net, kwolf@redhat.com,
	berrange@redhat.com, mreitz@redhat.com,
	ross.lagerwall@citrix.com, marcandre.lureau@gmail.com,
	pbonzini@redhat.com
Subject: [PATCH v8 13/20] multi-process: PCI BAR read/write handling for proxy & remote endpoints
Date: Fri, 31 Jul 2020 14:20:20 -0400	[thread overview]
Message-ID: <3588624b278c97cb3c9d1eeda109ad36af39effc.1596217462.git.jag.raman@oracle.com> (raw)
In-Reply-To: <cover.1596217462.git.jag.raman@oracle.com>
In-Reply-To: <cover.1596217462.git.jag.raman@oracle.com>

Proxy device object implements handler for PCI BAR writes and reads.
The handler uses BAR_WRITE/BAR_READ message to communicate to the
remote process with the BAR address and value to be written/read.
The remote process implements handler for BAR_WRITE/BAR_READ
message.

Signed-off-by: Jagannathan Raman <jag.raman@oracle.com>
Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com>
Signed-off-by: John G Johnson <john.g.johnson@oracle.com>
---
 hw/i386/remote-msg.c     | 88 ++++++++++++++++++++++++++++++++++++++++++++++++
 hw/pci/proxy.c           | 61 +++++++++++++++++++++++++++++++++
 include/hw/pci/proxy.h   | 16 +++++++--
 include/io/mpqemu-link.h | 10 ++++++
 io/mpqemu-link.c         |  6 ++++
 5 files changed, 179 insertions(+), 2 deletions(-)

diff --git a/hw/i386/remote-msg.c b/hw/i386/remote-msg.c
index c5b8651..7ccdd63 100644
--- a/hw/i386/remote-msg.c
+++ b/hw/i386/remote-msg.c
@@ -16,11 +16,14 @@
 #include "qapi/error.h"
 #include "sysemu/runstate.h"
 #include "hw/pci/pci.h"
+#include "exec/memattrs.h"
 
 static void process_config_write(QIOChannel *ioc, PCIDevice *dev,
                                  MPQemuMsg *msg);
 static void process_config_read(QIOChannel *ioc, PCIDevice *dev,
                                 MPQemuMsg *msg);
+static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp);
+static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp);
 
 gboolean mpqemu_process_msg(QIOChannel *ioc, GIOCondition cond,
                             gpointer opaque)
@@ -58,6 +61,12 @@ gboolean mpqemu_process_msg(QIOChannel *ioc, GIOCondition cond,
     case PCI_CONFIG_READ:
         process_config_read(ioc, pci_dev, &msg);
         break;
+    case BAR_WRITE:
+        process_bar_write(ioc, &msg, &local_err);
+        break;
+    case BAR_READ:
+        process_bar_read(ioc, &msg, &local_err);
+        break;
     default:
         error_setg(&local_err,
                    "Unknown command (%d) received for device %s (pid=%d)",
@@ -127,3 +136,82 @@ static void process_config_read(QIOChannel *ioc, PCIDevice *dev,
     }
 
 }
+
+static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp)
+{
+    BarAccessMsg *bar_access = &msg->data1.bar_access;
+    AddressSpace *as =
+        bar_access->memory ? &address_space_memory : &address_space_io;
+    MPQemuMsg ret = { 0 };
+    MemTxResult res;
+    uint64_t val;
+    Error *local_err = NULL;
+
+    if (!is_power_of_2(bar_access->size) ||
+       (bar_access->size > sizeof(uint64_t))) {
+        ret.data1.u64 = UINT64_MAX;
+        goto fail;
+    }
+
+    val = cpu_to_le64(bar_access->val);
+
+    res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED,
+                           (void *)&val, bar_access->size, true);
+
+    if (res != MEMTX_OK) {
+        error_setg(errp, "Could not perform address space write operation,"
+                   " inaccessible address: %lx in pid %d.",
+                   bar_access->addr, getpid());
+        ret.data1.u64 = -1;
+    }
+
+fail:
+    ret.cmd = RET_MSG;
+    ret.size = sizeof(ret.data1);
+
+    mpqemu_msg_send(&ret, ioc, &local_err);
+    if (local_err) {
+        error_setg(errp, "Error while sending message to proxy "
+                   "in remote process pid=%d", getpid());
+    }
+}
+
+static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp)
+{
+    BarAccessMsg *bar_access = &msg->data1.bar_access;
+    MPQemuMsg ret = { 0 };
+    AddressSpace *as;
+    MemTxResult res;
+    uint64_t val = 0;
+    Error *local_err = NULL;
+
+    as = bar_access->memory ? &address_space_memory : &address_space_io;
+
+    if (!is_power_of_2(bar_access->size) ||
+       (bar_access->size > sizeof(uint64_t))) {
+        val = UINT64_MAX;
+        goto fail;
+    }
+
+    res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED,
+                           (void *)&val, bar_access->size, false);
+
+    if (res != MEMTX_OK) {
+        error_setg(errp, "Could not perform address space read operation,"
+                   " inaccessible address: %lx in pid %d.",
+                   bar_access->addr, getpid());
+        val = UINT64_MAX;
+        goto fail;
+    }
+
+fail:
+    ret.cmd = RET_MSG;
+    ret.data1.u64 = le64_to_cpu(val);
+    ret.size = sizeof(ret.data1);
+
+    mpqemu_msg_send(&ret, ioc, &local_err);
+    if (local_err) {
+        error_setg(errp, "Error while sending message to proxy "
+                   "in remote process pid=%d", getpid());
+    }
+}
diff --git a/hw/pci/proxy.c b/hw/pci/proxy.c
index 945cc35..179f0c7 100644
--- a/hw/pci/proxy.c
+++ b/hw/pci/proxy.c
@@ -133,3 +133,64 @@ static void pci_proxy_dev_register_types(void)
 }
 
 type_init(pci_proxy_dev_register_types)
+
+static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr,
+                                bool write, hwaddr addr, uint64_t *val,
+                                unsigned size, bool memory)
+{
+    MPQemuMsg msg = { 0 };
+    long ret = -EINVAL;
+    Error *local_err = NULL;
+
+    msg.bytestream = 0;
+    msg.size = sizeof(msg.data1);
+    msg.data1.bar_access.addr = mr->addr + addr;
+    msg.data1.bar_access.size = size;
+    msg.data1.bar_access.memory = memory;
+
+    if (write) {
+        msg.cmd = BAR_WRITE;
+        msg.data1.bar_access.val = *val;
+    } else {
+        msg.cmd = BAR_READ;
+    }
+
+    ret = mpqemu_msg_send_and_await_reply(&msg, pdev->ioc, &local_err);
+    if (local_err) {
+        error_report("Failed to send BAR command to the remote process.");
+    }
+
+    if (!write) {
+        *val = ret;
+    }
+}
+
+static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val,
+                            unsigned size)
+{
+    ProxyMemoryRegion *pmr = opaque;
+
+    send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size,
+                        pmr->memory);
+}
+
+static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size)
+{
+    ProxyMemoryRegion *pmr = opaque;
+    uint64_t val;
+
+    send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size,
+                        pmr->memory);
+
+    return val;
+}
+
+const MemoryRegionOps proxy_mr_ops = {
+    .read = proxy_bar_read,
+    .write = proxy_bar_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 1,
+        .max_access_size = 1,
+    },
+};
diff --git a/include/hw/pci/proxy.h b/include/hw/pci/proxy.h
index 0a66ddc..9d57483 100644
--- a/include/hw/pci/proxy.h
+++ b/include/hw/pci/proxy.h
@@ -17,10 +17,22 @@
 #define PCI_PROXY_DEV(obj) \
             OBJECT_CHECK(PCIProxyDev, (obj), TYPE_PCI_PROXY_DEV)
 
-typedef struct PCIProxyDev {
+typedef struct PCIProxyDev PCIProxyDev;
+
+typedef struct ProxyMemoryRegion {
+    PCIProxyDev *dev;
+    MemoryRegion mr;
+    bool memory;
+    bool present;
+    uint8_t type;
+} ProxyMemoryRegion;
+
+struct PCIProxyDev {
     PCIDevice parent_dev;
     char *fd;
     QIOChannel *ioc;
-} PCIProxyDev;
+
+    ProxyMemoryRegion region[PCI_NUM_REGIONS];
+};
 
 #endif /* PROXY_H */
diff --git a/include/io/mpqemu-link.h b/include/io/mpqemu-link.h
index 9bd754e..ee3b44f 100644
--- a/include/io/mpqemu-link.h
+++ b/include/io/mpqemu-link.h
@@ -36,6 +36,8 @@ typedef enum {
     RET_MSG,
     PCI_CONFIG_WRITE,
     PCI_CONFIG_READ,
+    BAR_WRITE,
+    BAR_READ,
     MAX = INT_MAX,
 } MPQemuCmd;
 
@@ -51,6 +53,13 @@ typedef struct {
     int l;
 } ConfDataMsg;
 
+typedef struct {
+    hwaddr addr;
+    uint64_t val;
+    unsigned size;
+    bool memory;
+} BarAccessMsg;
+
 /**
  * Maximum size of data2 field in the message to be transmitted.
  */
@@ -78,6 +87,7 @@ typedef struct {
     union {
         uint64_t u64;
         SyncSysmemMsg sync_sysmem;
+        BarAccessMsg bar_access;
     } data1;
 
     int fds[REMOTE_MAX_FDS];
diff --git a/io/mpqemu-link.c b/io/mpqemu-link.c
index 5d04b81..82b8465 100644
--- a/io/mpqemu-link.c
+++ b/io/mpqemu-link.c
@@ -269,6 +269,12 @@ bool mpqemu_msg_valid(MPQemuMsg *msg)
             return false;
         }
         break;
+    case BAR_WRITE:
+    case BAR_READ:
+        if ((msg->size != sizeof(msg->data1)) || (msg->num_fds != 0)) {
+            return false;
+        }
+        break;
     default:
         break;
     }
-- 
1.8.3.1



  parent reply	other threads:[~2020-07-31 18:29 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-31 18:20 [PATCH v8 00/20] Initial support for multi-process qemu Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 01/20] memory: alloc RAM from file at offset Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 02/20] multi-process: Add config option for multi-process QEMU Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 03/20] multi-process: setup PCI host bridge for remote device Jagannathan Raman
2020-08-04 10:47   ` Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 04/20] multi-process: setup a machine object for remote device process Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 05/20] multi-process: add qio channel function to transmit Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 06/20] multi-process: define MPQemuMsg format and transmission functions Jagannathan Raman
2020-08-04 12:49   ` Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 07/20] multi-process: add co-routines to communicate with remote Jagannathan Raman
2020-08-10 16:02   ` Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 08/20] multi-process: Initialize message handler in remote device Jagannathan Raman
2020-08-04 12:58   ` Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 09/20] multi-process: Associate fd of a PCIDevice with its object Jagannathan Raman
2020-08-07 16:02   ` Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 10/20] multi-process: setup memory manager for remote device Jagannathan Raman
2020-08-10 15:27   ` Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 11/20] multi-process: introduce proxy object Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 12/20] multi-process: Forward PCI config space acceses to the remote process Jagannathan Raman
2020-07-31 18:20 ` Jagannathan Raman [this message]
2020-08-11 14:04   ` [PATCH v8 13/20] multi-process: PCI BAR read/write handling for proxy & remote endpoints Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 14/20] multi-process: Synchronize remote memory Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 15/20] multi-process: create IOHUB object to handle irq Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 16/20] multi-process: Retrieve PCI info from remote process Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 17/20] multi-process: heartbeat messages to remote Jagannathan Raman
2020-08-11 14:41   ` Stefan Hajnoczi
2020-08-14 23:01     ` Elena Ufimtseva
2020-08-19  8:00       ` Stefan Hajnoczi
2020-07-31 18:20 ` [PATCH v8 18/20] multi-process: perform device reset in the remote process Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 19/20] multi-process: add the concept description to docs/devel/qemu-multiprocess Jagannathan Raman
2020-07-31 18:20 ` [PATCH v8 20/20] multi-process: add configure and usage information Jagannathan Raman
2020-08-11 14:56 ` [PATCH v8 00/20] Initial support for multi-process qemu Stefan Hajnoczi

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