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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v3 1/8] target/riscv: Fix the PMP is locked check when using TOR
Date: Tue, 13 Apr 2021 12:41:43 +1000	[thread overview]
Message-ID: <358acc99b748a2099f460fb01d7f0727bdf1432e.1618281655.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1618281655.git.alistair.francis@wdc.com>

The RISC-V spec says:
    if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
    pmpaddri-1 are ignored.

The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.

Update the pmp_is_locked() function to not check the supporting fields
and instead enforce the lock functionality in the pmpaddr write operation.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/pmp.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index cff020122a..a3b253bb15 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -59,16 +59,6 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
         return 0;
     }
 
-    /* In TOR mode, need to check the lock bit of the next pmp
-     * (if there is a next)
-     */
-    const uint8_t a_field =
-        pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
-    if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
-         (PMP_AMATCH_TOR == a_field)) {
-        return 1;
-    }
-
     return 0;
 }
 
@@ -380,7 +370,23 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val)
 {
     trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
+
     if (addr_index < MAX_RISCV_PMPS) {
+        /*
+         * In TOR mode, need to check the lock bit of the next pmp
+         * (if there is a next).
+         */
+        if (addr_index + 1 < MAX_RISCV_PMPS) {
+            uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
+
+            if (pmp_cfg & PMP_LOCK &&
+                PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "ignoring pmpaddr write - pmpcfg + 1 locked\n");
+                return;
+            }
+        }
+
         if (!pmp_is_locked(env, addr_index)) {
             env->pmp_state.pmp[addr_index].addr_reg = val;
             pmp_update_rule(env, addr_index);
-- 
2.31.1



  reply	other threads:[~2021-04-13  2:44 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-13  2:41 [PATCH v3 0/8] RISC-V: Add support for ePMP v0.9.1 Alistair Francis
2021-04-13  2:41 ` Alistair Francis [this message]
2021-04-13  2:41 ` [PATCH v3 2/8] target/riscv: Define ePMP mseccfg Alistair Francis
2021-04-13  2:42 ` [PATCH v3 3/8] target/riscv: Add the ePMP feature Alistair Francis
2021-04-13  2:42 ` [PATCH v3 4/8] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-04-13  2:42 ` [PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-04-14  7:35   ` Bin Meng
2021-04-15  4:17     ` Alistair Francis
2021-04-13  2:42 ` [PATCH v3 6/8] target/riscv: Add a config option for ePMP Alistair Francis
2021-04-13  2:42 ` [PATCH v3 7/8] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-04-13  2:43 ` [PATCH v3 8/8] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis

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