From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: Re: [PATCH v2 0/2] target/arm: Fix tlb flush page vs tbi
Date: Sat, 17 Oct 2020 11:01:07 +0200 [thread overview]
Message-ID: <365059bf-a091-327f-dd09-2e134e3dc547@amsat.org> (raw)
In-Reply-To: <20201016210754.818257-1-richard.henderson@linaro.org>
On 10/16/20 11:07 PM, Richard Henderson wrote:
> Since the FAR_ELx fix at 38d931687fa1, it is reported that
> page granularity flushing is broken.
>
> This makes sense, since TCG will record the entire virtual
> address in its TLB, not simply the 56 significant bits.
> With no other TCG support, the ARM backend should require
> 256 different page flushes to clear the virtual address of
> any possible tag.
>
> So I added a new tcg interface that allows passing the size
> of the virtual address. I thought a simple bit-count was a
> cleaner interface than passing in a mask, since it means that
> we couldn't be passed nonsensical masks like 0xdeadbeef. It
> also makes it easy to re-direct special cases.
Series:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
next prev parent reply other threads:[~2020-10-17 9:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-16 21:07 [PATCH v2 0/2] target/arm: Fix tlb flush page vs tbi Richard Henderson
2020-10-16 21:07 ` [PATCH v2 1/2] accel/tcg: Add tlb_flush_page_bits_by_mmuidx* Richard Henderson
2020-10-16 21:40 ` Peter Maydell
2020-10-16 21:07 ` [PATCH v2 2/2] target/arm: Use tlb_flush_page_bits_by_mmuidx* Richard Henderson
2020-10-17 9:01 ` Philippe Mathieu-Daudé [this message]
2020-10-19 15:47 ` [PATCH v2 0/2] target/arm: Fix tlb flush page vs tbi Peter Maydell
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