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([2001:b07:6468:f312:c0e4:dcf4:b543:ce19]) by smtp.gmail.com with ESMTPSA id w18sm1678274wrl.75.2019.10.22.09.50.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Oct 2019 09:50:34 -0700 (PDT) Subject: Re: [PATCH RESEND v6 0/2] x86: Enable user wait instructions To: Tao Xu , rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com References: <20191011074103.30393-1-tao3.xu@intel.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: <393ea49d-1da3-9454-eae3-f8393a6ce72b@redhat.com> Date: Tue, 22 Oct 2019 18:50:33 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20191011074103.30393-1-tao3.xu@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/10/19 09:41, Tao Xu wrote: > UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. >=20 > UMONITOR arms address monitoring hardware using an address. A store > to an address within the specified address range triggers the > monitoring hardware to wake up the processor waiting in umwait. >=20 > UMWAIT instructs the processor to enter an implementation-dependent > optimized state while monitoring a range of addresses. The optimized > state may be either a light-weight power/performance optimized state > (c0.1 state) or an improved power/performance optimized state > (c0.2 state). >=20 > TPAUSE instructs the processor to enter an implementation-dependent > optimized state c0.1 or c0.2 state and wake up when time-stamp counter > reaches specified timeout. >=20 > Availability of the user wait instructions is indicated by the presence > of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. >=20 > The patches enable the umonitor, umwait and tpause features in KVM. > Because umwait and tpause can put a (psysical) CPU into a power saving > state, by default we dont't expose it in kvm and provide a capability t= o > enable it. Use kvm capability to enable UMONITOR, UMWAIT and TPAUSE whe= n > QEMU use "-overcommit cpu-pm=3Don, a VM can use UMONITOR, UMWAIT and TP= AUSE > instructions. If the instruction causes a delay, the amount of time > delayed is called here the physical delay. The physical delay is first > computed by determining the virtual delay (the time to delay relative t= o > the VM=E2=80=99s timestamp counter). Otherwise, UMONITOR, UMWAIT and TP= AUSE cause > an invalid-opcode exception(#UD). >=20 > The release document ref below link: > https://software.intel.com/sites/default/files/\ > managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf >=20 > Changelog: > v6: > Remove CPUID_7_0_ECX_WAITPKG if enable_cpu_pm is not set. > (Paolo) >=20 > Tao Xu (2): > x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE > target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR >=20 > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 3 +++ > target/i386/kvm.c | 19 +++++++++++++++++++ > target/i386/machine.c | 20 ++++++++++++++++++++ > 4 files changed, 43 insertions(+), 1 deletion(-) >=20 Queued, thanks. Paolo