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[97.113.2.33]) by smtp.gmail.com with ESMTPSA id g5sm343765pjt.14.2019.06.17.16.29.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 16:29:30 -0700 (PDT) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= References: <20190614171200.21078-1-alex.bennee@linaro.org> <20190614171200.21078-2-alex.bennee@linaro.org> <68f400ee-9186-f1f7-687d-9c96bde89c7d@linaro.org> <87y320wrif.fsf@zen.linaroharston> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <3aa14040-26de-fe61-2578-46a2772347c7@linaro.org> Date: Mon, 17 Jun 2019 16:29:15 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <87y320wrif.fsf@zen.linaroharston> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: Re: [Qemu-devel] [PATCH v3 01/50] trace: expand mem_info:size_shift to 3 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Emilio G. Cota" , qemu-devel@nongnu.org, Stefan Hajnoczi Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/17/19 1:22 AM, Alex Bennée wrote: > > Richard Henderson writes: > >> On 6/14/19 10:11 AM, Alex Bennée wrote: >>> From: "Emilio G. Cota" >>> >>> This will allow us to trace 16B-long memory accesses. >>> >>> Reviewed-by: Alex Bennée >>> Signed-off-by: Emilio G. Cota >>> --- >>> trace-events | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/trace-events b/trace-events >>> index 844ee58dd9..037169aab3 100644 >>> --- a/trace-events >>> +++ b/trace-events >>> @@ -159,7 +159,7 @@ vcpu guest_cpu_reset(void) >>> # Access information can be parsed as: >>> # >>> # struct mem_info { >>> -# uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes */ >>> +# uint8_t size_shift : 3; /* interpreted as "1 << size_shift" bytes */ >>> # bool sign_extend: 1; /* sign-extended */ >>> # uint8_t endianness : 1; /* 0: little, 1: big */ >>> # bool store : 1; /* wheter it's a store operation */ >>> >> >> Well, 128B-long memory accesses. But SVE supports 256B memory accesses >> already. So why not add one more bit now. > > Good point. > > Do we have any architectures that do load/stores that are not power of > 2? I guess the SVE non-faulting accesses are treated as a series of elem > size accesses. Yes, non-faults are in addition predicated, so each element is considered individually. Even the SVE non-predicated load/stores can technically be considered a sequence of byte operations. Which, I suppose could be helpful, because SVE can otherwise be configured to do non-power-of-2 operations. r~