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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 25 Feb 2020 15:00:18 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01PF0Hcn49676312 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 25 Feb 2020 15:00:17 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8F5AA52082; Tue, 25 Feb 2020 15:00:17 +0000 (GMT) Received: from oc7455500831.ibm.com (unknown [9.145.53.31]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 5C2E15204F; Tue, 25 Feb 2020 15:00:17 +0000 (GMT) Subject: Re: [PATCH] pc-bios/s390x: Pack ResetInfo struct To: jjherne@linux.ibm.com, qemu-devel@nongnu.org, qemu-s390x@nongnu.org, cohuck@redhat.com References: <20200205182126.13010-1-jjherne@linux.ibm.com> <941cc201-4c33-0ad3-ecc8-eab2709d350d@de.ibm.com> <91910082-ffeb-c588-7434-3de5fbfcbfa6@linux.ibm.com> <29aece69-3b53-6c46-f295-cbc4bf93ff95@linux.ibm.com> From: Christian Borntraeger Autocrypt: addr=borntraeger@de.ibm.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <29aece69-3b53-6c46-f295-cbc4bf93ff95@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-TM-AS-GCONF: 00 x-cbid: 20022515-0008-0000-0000-000003564FF3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20022515-0009-0000-0000-00004A776BFC Message-Id: <3dad5712-686f-c05a-b085-d7ee4c389b3c@de.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-25_05:2020-02-21, 2020-02-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 bulkscore=0 mlxlogscore=831 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002250118 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id 01PExDKm095773 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 25.02.20 13:58, Jason J. Herne wrote: > On 2/25/20 6:13 AM, Christian Borntraeger wrote: >> >> >> On 25.02.20 11:23, Jason J. Herne wrote: >>> On 2/13/20 1:24 PM, Christian Borntraeger wrote: >>> ... >>>>>> diff --git a/pc-bios/s390-ccw/jump2ipl.c b/pc-bios/s390-ccw/jump2i= pl.c >>>>>> index da13c43cc0..8839226803 100644 >>>>>> --- a/pc-bios/s390-ccw/jump2ipl.c >>>>>> +++ b/pc-bios/s390-ccw/jump2ipl.c >>>>>> @@ -18,6 +18,7 @@ >>>>>> =C2=A0=C2=A0=C2=A0 typedef struct ResetInfo { >>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 uint64_t ipl_psw; >>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 uint32_t ipl_continue; >>>>>> +=C2=A0=C2=A0=C2=A0 uint32_t pad; >>>>>> =C2=A0=C2=A0=C2=A0 } ResetInfo; >>>>>> =C2=A0=C2=A0=C2=A0 =C2=A0 static ResetInfo save; >>>>>> >>>>>> >>>>>> also work? If yes, both variants are valid. Either packed or expli= cit padding. >>>>>> >>>>> >>>>> I don't believe this will work. I think the problem is that we're o= verwriting too much memory when we cast address 0 as a ResetInfo and then= overwrite it (*current =3D save). I think we need the struct to be sized= at 12-bytes instead of 16. >>>>> >>>> >>>> The idea of the code is that we _save_ the original content from add= ress 0 to save and _restore_ it before jumping into final code. I do not = yet understand why this does not work. >>>> >>> >>> I've found the real problem here. Legacy operating systems that expec= t to start >>> in 32-bit addressing mode can fail if we leave junk in the high halve= s of our >>> 64-bit registers. This is because some instructions (LA for example) = are >>> bi-modal and operate differently depending on the machine's current a= ddressing >>> mode. >>> >>> In the case where we pack the struct, the compiler happens to use the= mvc >>> instruction to load/store the current/save memory areas. >>> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *current =3D save; >>> =C2=A0=C2=A0 1fc:=C2=A0=C2=A0=C2=A0 e3 10 b0 a8 00 04=C2=A0=C2=A0=C2=A0= =C2=A0 lg=C2=A0=C2=A0=C2=A0 %r1,168(%r11) >>> =C2=A0=C2=A0 202:=C2=A0=C2=A0=C2=A0 c0 20 00 00 00 00=C2=A0=C2=A0=C2=A0= =C2=A0 larl=C2=A0=C2=A0=C2=A0 %r2,202 >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 204: R_390_PC32DBL=C2=A0=C2=A0=C2=A0 .bss+0x2 >>> =C2=A0=C2=A0 208:=C2=A0=C2=A0=C2=A0 d2 0b 10 00 20 00=C2=A0=C2=A0=C2=A0= =C2=A0 mvc=C2=A0=C2=A0=C2=A0 0(12,%r1),0(%r2) >>> >>> Everything works as expected here, our legacy OS boots without issue. >>> However, in the case where we've packed this struct the compiler opti= mizes the >>> code and uses lmg/stmg instead of mvc to copy the data: >>> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *current =3D save; >>> =C2=A0=C2=A0 1fc:=C2=A0=C2=A0=C2=A0 e3 10 b0 a8 00 04=C2=A0=C2=A0=C2=A0= =C2=A0 lg=C2=A0=C2=A0=C2=A0 %r1,168(%r11) >>> =C2=A0=C2=A0 202:=C2=A0=C2=A0=C2=A0 c0 20 00 00 00 00=C2=A0=C2=A0=C2=A0= =C2=A0 larl=C2=A0=C2=A0=C2=A0 %r2,202 >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 204: R_390_PC32DBL=C2=A0=C2=A0=C2=A0 .bss+0x2 >>> =C2=A0=C2=A0 208:=C2=A0=C2=A0=C2=A0 eb 23 20 00 00 04=C2=A0=C2=A0=C2=A0= =C2=A0 lmg=C2=A0=C2=A0=C2=A0 %r2,%r3,0(%r2) >>> =C2=A0=C2=A0 20e:=C2=A0=C2=A0=C2=A0 eb 23 10 00 00 24=C2=A0=C2=A0=C2=A0= =C2=A0 stmg=C2=A0=C2=A0=C2=A0 %r2,%r3,0(%r1) >>> >>> Depending on the data being copied, the high halves of the registers = may contain >>> non-zero values. Example: >>> >>> =C2=A0=C2=A0=C2=A0=C2=A0 r2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0x108000080000780=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 74309395999098752 >>> =C2=A0=C2=A0=C2=A0=C2=A0 r3=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0x601001800004368=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 432627142283510632 >>> >>> So, by sheer luck of the generated assembler, the patch happens to "f= ix" the >>> problem.=C2=A0 A real fix might be to insert inline assembler that cl= ears the high >>> halves of the registers before we call ipl() in jump_to_IPL_2(). Can = we think of >>> a better way to do that than 15 LLGTR instructions? :) Let me know yo= ur >>> thoughts >> >> Does sam31 before the ipl() work? > asm volatile ("sam31\n"); >=20 > Inserting the above right before ipl(); does not change the outcome, th= e guest still fails. >=20 > This allows the guest to boot. >=20 > asm volatile ("llgtr %r2,%r2\n" > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 "llgtr %r3,%r3\n"); >=20 > My guess as to why sam31 does not work: The legacy OS is eventually doi= ng a sam64 and the high halves of the registers are not subsequently clea= red before use. I could be wrong about this though. I think we should rewrite jump_to_IPL_2 is assembler as we cannot clear o= ut all registers with just inline assembly (we whould kill the stack and others that the c= ompiler might still want). Do the register clearing in there and then use something like static void jump_to_IPL_2(void) { asm volatile( ....clearing... "llgf 14,8\n" "br 14\n"); }