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[189.204.159.168]) by smtp.gmail.com with ESMTPSA id g6sm36393oov.19.2020.12.01.08.11.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Dec 2020 08:11:45 -0800 (PST) Subject: Re: [PATCH v2 26/28] hw/intc/armv7m_nvic: Implement read/write for RAS register block To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20201119215617.29887-1-peter.maydell@linaro.org> <20201119215617.29887-27-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <3e3d8da6-0e0b-a064-85b3-895de539fc08@linaro.org> Date: Tue, 1 Dec 2020 10:11:42 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201119215617.29887-27-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/19/20 3:56 PM, Peter Maydell wrote: > The RAS feature has a block of memory-mapped registers at offset > 0x5000 within the PPB. For a "minimal RAS" implementation we provide > no error records and so the only registers that exist in the block > are ERRIIDR and ERRDEVID. > > The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour > of the "nvic-default" region is actually valid for minimal-RAS, > so the main benefit of providing an explicit implementation of > the register block is more accurate LOG_UNIMP messages, and a > framework for where we could add a real RAS implementation later > if necessary. > > Signed-off-by: Peter Maydell > --- > include/hw/intc/armv7m_nvic.h | 1 + > hw/intc/armv7m_nvic.c | 56 +++++++++++++++++++++++++++++++++++ > 2 files changed, 57 insertions(+) Reviewed-by: Richard Henderson r~