From: Guenter Roeck <linux@roeck-us.net>
To: QEMU Developers <qemu-devel@nongnu.org>
Cc: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Michael S. Tsirkin" <mst@redhat.com>
Subject: Problems with irq mapping in qemu v5.2
Date: Tue, 22 Dec 2020 08:16:41 -0800 [thread overview]
Message-ID: <3f0f8fc6-6148-a76e-1088-b7882b0bbcaf@roeck-us.net> (raw)
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to pci_bus_change_irq_level(). That makes sense, given that bus->irq_count
is indexed and sized by the number of interrupts.
However, as it turns out, the interrupt number passed to this function
is the _mapped_ interrupt number. The result in assertion failures for various
emulations.
Examples (I don't know if there are others):
- ppc4xx_pci_map_irq() maps the interrupt number to "slot - 1". Obviously
that isn't a good thing to do for slot 0, and indeed results in an
assertion as soon as slot 0 is initialized (presumably that is the root
bridge). Changing the mapping to "slot" doesn't help because valid slots
are 0..4, and only four interrupts are allocated.
- pci_bonito_map_irq() changes the mapping all over the place. Whatever
it does, it returns numbers starting with 32 for slots 5..12. With
a total number of 32 interrupts, this again results in an assertion
failure.
ppc4xx_pci_map_irq() is definitely buggy. I just don't know what the
correct mapping should be. slot & 3, maybe ?
I don't really have a good solution for pci_bonito_map_irq(). It may not
matter much - I have not been able to boot fuloong_2e since qemu v4.0,
and afaics that is the only platform using it. Maybe it is just completely
broken ?
Thanks,
Guenter
next reply other threads:[~2020-12-22 16:19 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-22 16:16 Guenter Roeck [this message]
2020-12-22 17:55 ` Problems with irq mapping in qemu v5.2 BALATON Zoltan via
2020-12-22 22:23 ` BALATON Zoltan via
2020-12-22 23:12 ` Guenter Roeck
2020-12-23 10:31 ` Mark Cave-Ayland
2020-12-23 13:39 ` BALATON Zoltan via
2020-12-22 18:23 ` Mark Cave-Ayland
2020-12-22 21:23 ` Guenter Roeck
2020-12-22 22:57 ` BALATON Zoltan via
2020-12-23 1:01 ` Guenter Roeck
2020-12-23 13:35 ` BALATON Zoltan via
2020-12-23 10:17 ` Mark Cave-Ayland
2020-12-23 10:24 ` Mark Cave-Ayland
2020-12-23 13:17 ` BALATON Zoltan via
2020-12-23 18:15 ` Mark Cave-Ayland
2020-12-25 23:43 ` BALATON Zoltan via
2020-12-31 15:34 ` Peter Maydell
2020-12-23 15:21 ` Philippe Mathieu-Daudé
2020-12-23 16:09 ` Mark Cave-Ayland
2020-12-23 17:01 ` Guenter Roeck
2020-12-23 18:01 ` Mark Cave-Ayland
2020-12-23 20:20 ` BALATON Zoltan via
2020-12-23 21:01 ` Guenter Roeck
2020-12-23 22:05 ` Mark Cave-Ayland
2020-12-23 22:47 ` Guenter Roeck
2020-12-23 23:05 ` Philippe Mathieu-Daudé
2020-12-23 23:56 ` BALATON Zoltan via
2020-12-24 1:34 ` BALATON Zoltan via
2020-12-24 2:29 ` Jiaxun Yang
2020-12-24 5:32 ` Guenter Roeck
2020-12-24 8:11 ` BALATON Zoltan via
2020-12-24 10:50 ` Philippe Mathieu-Daudé
2020-12-24 17:09 ` BALATON Zoltan via
2020-12-28 19:26 ` Mark Cave-Ayland
2020-12-28 21:18 ` BALATON Zoltan via
2020-12-23 19:49 ` BALATON Zoltan via
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