* [PATCH v14 01/22] cpu: Introduce TCGCpuOperations struct
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
@ 2021-01-28 9:27 ` Claudio Fontana
2021-01-28 9:27 ` [PATCH v14 02/22] target/riscv: remove CONFIG_TCG, as it is always TCG Claudio Fontana
` (21 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:27 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: make the tcg code build for CONFIG_TCG only]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: move TCGCpuOperations inside include/hw/core/cpu.h]
---
include/hw/core/cpu.h | 20 +++++++++++++++++++-
cpu.c | 6 +++++-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 12 ++++++------
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 52 insertions(+), 30 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 140fa32a5e..5b981c1730 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,6 +76,21 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
+#ifdef CONFIG_TCG
+/**
+ * struct TcgCpuOperations: TCG operations specific to a CPU class
+ */
+typedef struct TcgCpuOperations {
+ /**
+ * @initialize: Initalize TCG state
+ *
+ * Called when the first CPU is realized.
+ */
+ void (*initialize)(void);
+
+} TcgCpuOperations;
+#endif /* CONFIG_TCG */
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -222,12 +237,15 @@ struct CPUClass {
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
- void (*tcg_initialize)(void);
const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+
+#ifdef CONFIG_TCG
+ TcgCpuOperations tcg_ops;
+#endif /* CONFIG_TCG */
};
/*
diff --git a/cpu.c b/cpu.c
index 0b245cda2e..79a2bf12b3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -159,14 +159,18 @@ void cpu_exec_initfn(CPUState *cpu)
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+#ifdef CONFIG_TCG
static bool tcg_target_initialized;
+#endif /* CONFIG_TCG */
cpu_list_add(cpu);
+#ifdef CONFIG_TCG
if (tcg_enabled() && !tcg_target_initialized) {
tcg_target_initialized = true;
- cc->tcg_initialize();
+ cc->tcg_ops.initialize();
}
+#endif /* CONFIG_TCG */
tlb_init(cpu);
qemu_plugin_vcpu_init_hook(cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b3fd6643e8..d66f0351a9 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -231,7 +231,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
- cc->tcg_initialize = alpha_translate_init;
+ cc->tcg_ops.initialize = alpha_translate_init;
cc->gdb_num_core_regs = 67;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 40142ac141..fa4d4ba4eb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2276,7 +2276,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = arm_translate_init;
+ cc->tcg_ops.initialize = arm_translate_init;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 6f3d5a9e4a..fb66695fbb 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -207,7 +207,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
- cc->tcg_initialize = avr_cpu_tcg_init;
+ cc->tcg_ops.initialize = avr_cpu_tcg_init;
cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index cff6b9eabf..4328f8e6c9 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -201,7 +201,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 8;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
@@ -212,7 +212,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 9;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
@@ -223,7 +223,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 10;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
@@ -234,7 +234,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 11;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
@@ -245,7 +245,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 17;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
@@ -284,7 +284,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
- cc->tcg_initialize = cris_initialize_tcg;
+ cc->tcg_ops.initialize = cris_initialize_tcg;
}
#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e28f047d10..80e3081631 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -154,7 +154,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
cc->disas_set_info = hppa_cpu_disas_set_info;
- cc->tcg_initialize = hppa_translate_init;
+ cc->tcg_ops.initialize = hppa_translate_init;
cc->gdb_num_core_regs = 128;
}
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 4fa013720e..d90502a0cc 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -64,7 +64,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
- cc->tcg_initialize = tcg_x86_init;
+ cc->tcg_ops.initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c50ad5fa15..ef795b81a4 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -237,7 +237,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
- cc->tcg_initialize = lm32_translate_init;
+ cc->tcg_ops.initialize = lm32_translate_init;
}
#define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b811a0bdde..3604ece49b 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -478,7 +478,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
dc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
- cc->tcg_initialize = m68k_tcg_init;
+ cc->tcg_ops.initialize = m68k_tcg_init;
cc->gdb_num_core_regs = 18;
}
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index d5e8bfe11f..f2978ca726 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -382,7 +382,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 32 + 27;
cc->disas_set_info = mb_disas_set_info;
- cc->tcg_initialize = mb_tcg_init;
+ cc->tcg_ops.initialize = mb_tcg_init;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4c4548233c..b96c3d5969 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -689,7 +689,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = mips_tcg_init;
+ cc->tcg_ops.initialize = mips_tcg_init;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 6e0443ccb7..224cfc8361 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -116,7 +116,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
- cc->tcg_initialize = moxie_translate_init;
+ cc->tcg_ops.initialize = moxie_translate_init;
}
static void moxielite_initfn(Object *obj)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 58688e1623..c28eb05ef0 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -234,7 +234,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
cc->gdb_num_core_regs = 49;
- cc->tcg_initialize = nios2_tcg_init;
+ cc->tcg_ops.initialize = nios2_tcg_init;
}
static const TypeInfo nios2_cpu_type_info = {
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index b0bdfbe4fe..a957f59e2e 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -198,7 +198,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
- cc->tcg_initialize = openrisc_translate_init;
+ cc->tcg_ops.initialize = openrisc_translate_init;
cc->disas_set_info = openrisc_disas_set_info;
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 27788021eb..567f6790a9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,7 +618,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
#ifdef CONFIG_TCG
- cc->tcg_initialize = riscv_translate_init;
+ cc->tcg_ops.initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
#endif
device_class_set_props(dc, riscv_cpu_properties);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 2bb14144a7..cdcab49c8a 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -195,7 +195,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
- cc->tcg_initialize = rx_translate_init;
+ cc->tcg_ops.initialize = rx_translate_init;
cc->tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7da70afbf2..890781e74c 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -515,7 +515,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = s390x_translate_init;
+ cc->tcg_ops.initialize = s390x_translate_init;
cc->tlb_fill = s390_cpu_tlb_fill;
#endif
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 1e0f05a15b..b86753cda5 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -232,7 +232,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
- cc->tcg_initialize = sh4_translate_init;
+ cc->tcg_ops.initialize = sh4_translate_init;
cc->gdb_num_core_regs = 59;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 6f14e370ed..3ab71e9d00 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -881,7 +881,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
- cc->tcg_initialize = sparc_tcg_init;
+ cc->tcg_ops.initialize = sparc_tcg_init;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_num_core_regs = 86;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 1fee87c094..cd24d0eb9d 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -153,7 +153,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = tilegx_cpu_set_pc;
cc->tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
- cc->tcg_initialize = tilegx_tcg_init;
+ cc->tcg_ops.initialize = tilegx_tcg_init;
}
static const TypeInfo tilegx_cpu_type_info = {
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 4bff1d4718..bf135af40f 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -164,7 +164,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = tricore_cpu_set_pc;
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
- cc->tcg_initialize = tricore_tcg_init;
+ cc->tcg_ops.initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index b27fb9689f..226bf4226e 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -137,7 +137,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->tcg_initialize = uc32_translate_init;
+ cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 88a32268a1..5a6f5bf88b 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -209,7 +209,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->tcg_initialize = xtensa_translate_init;
+ cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
}
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 3c05a17343..189f27cd1c 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10878,7 +10878,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
#ifdef CONFIG_TCG
- cc->tcg_initialize = ppc_translate_init;
+ cc->tcg_ops.initialize = ppc_translate_init;
cc->tlb_fill = ppc_cpu_tlb_fill;
#endif
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 02/22] target/riscv: remove CONFIG_TCG, as it is always TCG
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
2021-01-28 9:27 ` [PATCH v14 01/22] cpu: Introduce TCGCpuOperations struct Claudio Fontana
@ 2021-01-28 9:27 ` Claudio Fontana
2021-01-28 18:34 ` Alex Bennée
2021-01-28 9:27 ` [PATCH v14 03/22] accel/tcg: split TCG-only code from cpu_exec_realizefn Claudio Fontana
` (20 subsequent siblings)
22 siblings, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:27 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 567f6790a9..60d0b43153 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -617,10 +617,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
-#ifdef CONFIG_TCG
cc->tcg_ops.initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
-#endif
+
device_class_set_props(dc, riscv_cpu_properties);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v14 02/22] target/riscv: remove CONFIG_TCG, as it is always TCG
2021-01-28 9:27 ` [PATCH v14 02/22] target/riscv: remove CONFIG_TCG, as it is always TCG Claudio Fontana
@ 2021-01-28 18:34 ` Alex Bennée
0 siblings, 0 replies; 44+ messages in thread
From: Alex Bennée @ 2021-01-28 18:34 UTC (permalink / raw)
To: Claudio Fontana
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Richard Henderson, qemu-devel, Roman Bolshakov, Alistair Francis,
Paolo Bonzini, Philippe Mathieu-Daudé
Claudio Fontana <cfontana@suse.de> writes:
> for now only TCG is allowed as an accelerator for riscv,
> so remove the CONFIG_TCG use.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v14 03/22] accel/tcg: split TCG-only code from cpu_exec_realizefn
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
2021-01-28 9:27 ` [PATCH v14 01/22] cpu: Introduce TCGCpuOperations struct Claudio Fontana
2021-01-28 9:27 ` [PATCH v14 02/22] target/riscv: remove CONFIG_TCG, as it is always TCG Claudio Fontana
@ 2021-01-28 9:27 ` Claudio Fontana
2021-01-28 9:27 ` [PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops Claudio Fontana
` (19 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:27 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
move away TCG-only code, make it compile only on TCG.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h]
---
include/exec/cpu-all.h | 11 +++++--
include/hw/core/cpu.h | 2 ++
accel/tcg/cpu-exec.c | 28 +++++++++++++++++
cpu.c | 70 ++++++++++++++++++++----------------------
hw/core/cpu.c | 6 +++-
5 files changed, 77 insertions(+), 40 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 4b5408c341..cfb1d79331 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -410,19 +410,26 @@ static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr)
}
#ifdef CONFIG_TCG
+/* accel/tcg/cpu-exec.c */
void dump_drift_info(void);
+/* accel/tcg/translate-all.c */
void dump_exec_info(void);
void dump_opcount_info(void);
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
+#ifdef CONFIG_TCG
+/* accel/tcg/cpu-exec.c */
+int cpu_exec(CPUState *cpu);
+void tcg_exec_realizefn(CPUState *cpu, Error **errp);
+void tcg_exec_unrealizefn(CPUState *cpu);
+#endif /* CONFIG_TCG */
+
/* Returns: 0 on success, -1 on error */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
void *ptr, target_ulong len, bool is_write);
-int cpu_exec(CPUState *cpu);
-
/**
* cpu_set_cpustate_pointers(cpu)
* @cpu: The cpu object
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 5b981c1730..96fdca39d2 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1130,6 +1130,8 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
+
+/* $(top_srcdir)/cpu.c */
void cpu_exec_initfn(CPUState *cpu);
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
void cpu_exec_unrealizefn(CPUState *cpu);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 6d017e46dd..5628a156d1 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -828,6 +828,34 @@ int cpu_exec(CPUState *cpu)
return ret;
}
+void tcg_exec_realizefn(CPUState *cpu, Error **errp)
+{
+ static bool tcg_target_initialized;
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!tcg_target_initialized) {
+ cc->tcg_ops.initialize();
+ tcg_target_initialized = true;
+ }
+ tlb_init(cpu);
+ qemu_plugin_vcpu_init_hook(cpu);
+
+#ifndef CONFIG_USER_ONLY
+ tcg_iommu_init_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+}
+
+/* undo the initializations in reverse order */
+void tcg_exec_unrealizefn(CPUState *cpu)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_iommu_free_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+
+ qemu_plugin_vcpu_exit_hook(cpu);
+ tlb_destroy(cpu);
+}
+
#ifndef CONFIG_USER_ONLY
void dump_drift_info(void)
diff --git a/cpu.c b/cpu.c
index 79a2bf12b3..bfbe5a66f9 100644
--- a/cpu.c
+++ b/cpu.c
@@ -124,13 +124,35 @@ const VMStateDescription vmstate_cpu_common = {
};
#endif
+void cpu_exec_realizefn(CPUState *cpu, Error **errp)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cpu_list_add(cpu);
+
+#ifdef CONFIG_TCG
+ /* NB: errp parameter is unused currently */
+ if (tcg_enabled()) {
+ tcg_exec_realizefn(cpu, errp);
+ }
+#endif /* CONFIG_TCG */
+
+#ifdef CONFIG_USER_ONLY
+ assert(cc->vmsd == NULL);
+#else
+ if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+ vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
+ }
+ if (cc->vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ }
+#endif /* CONFIG_USER_ONLY */
+}
+
void cpu_exec_unrealizefn(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- tlb_destroy(cpu);
- cpu_list_remove(cpu);
-
#ifdef CONFIG_USER_ONLY
assert(cc->vmsd == NULL);
#else
@@ -140,8 +162,15 @@ void cpu_exec_unrealizefn(CPUState *cpu)
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
}
- tcg_iommu_free_notifier_list(cpu);
#endif
+#ifdef CONFIG_TCG
+ /* NB: errp parameter is unused currently */
+ if (tcg_enabled()) {
+ tcg_exec_unrealizefn(cpu);
+ }
+#endif /* CONFIG_TCG */
+
+ cpu_list_remove(cpu);
}
void cpu_exec_initfn(CPUState *cpu)
@@ -156,39 +185,6 @@ void cpu_exec_initfn(CPUState *cpu)
#endif
}
-void cpu_exec_realizefn(CPUState *cpu, Error **errp)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_TCG
- static bool tcg_target_initialized;
-#endif /* CONFIG_TCG */
-
- cpu_list_add(cpu);
-
-#ifdef CONFIG_TCG
- if (tcg_enabled() && !tcg_target_initialized) {
- tcg_target_initialized = true;
- cc->tcg_ops.initialize();
- }
-#endif /* CONFIG_TCG */
- tlb_init(cpu);
-
- qemu_plugin_vcpu_init_hook(cpu);
-
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else /* !CONFIG_USER_ONLY */
- if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
- vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
- }
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
- }
-
- tcg_iommu_init_notifier_list(cpu);
-#endif
-}
-
const char *parse_cpu_option(const char *cpu_option)
{
ObjectClass *oc;
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7553411653..57542b6906 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -199,6 +199,10 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
return target_words_bigendian();
}
+/*
+ * XXX the following #if is always true because this is a common_ss
+ * module, so target CONFIG_* is never defined.
+ */
#if !defined(CONFIG_USER_ONLY)
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
@@ -340,9 +344,9 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
static void cpu_common_unrealizefn(DeviceState *dev)
{
CPUState *cpu = CPU(dev);
+
/* NOTE: latest generic point before the cpu is fully unrealized */
trace_fini_vcpu(cpu);
- qemu_plugin_vcpu_exit_hook(cpu);
cpu_exec_unrealizefn(cpu);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (2 preceding siblings ...)
2021-01-28 9:27 ` [PATCH v14 03/22] accel/tcg: split TCG-only code from cpu_exec_realizefn Claudio Fontana
@ 2021-01-28 9:27 ` Claudio Fontana
2021-01-28 18:58 ` Alex Bennée
2021-01-28 9:27 ` [PATCH v14 05/22] cpu: Move cpu_exec_* " Claudio Fontana
` (18 subsequent siblings)
22 siblings, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:27 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/core/cpu.h | 20 +++++++++++---------
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 4 +++-
target/avr/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
13 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 96fdca39d2..b3c1bb77eb 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -87,6 +87,17 @@ typedef struct TcgCpuOperations {
* Called when the first CPU is realized.
*/
void (*initialize)(void);
+ /**
+ * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
+ *
+ * This is called when we abandon execution of a TB before
+ * starting it, and must set all parts of the CPU state which
+ * the previous TB in the chain may not have updated. This
+ * will need to do more. If this hook is not implemented then
+ * the default is to call @set_pc(tb->pc).
+ */
+ void (*synchronize_from_tb)(CPUState *cpu,
+ const struct TranslationBlock *tb);
} TcgCpuOperations;
#endif /* CONFIG_TCG */
@@ -121,13 +132,6 @@ typedef struct TcgCpuOperations {
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @synchronize_from_tb: Callback for synchronizing state from a TCG
- * #TranslationBlock. This is called when we abandon execution
- * of a TB before starting it, and must set all parts of the CPU
- * state which the previous TB in the chain may not have updated.
- * This always includes at least the program counter; some targets
- * will need to do more. If this hook is not implemented then the
- * default is to call @set_pc(tb->pc).
* @tlb_fill: Callback for handling a softmmu tlb miss or user-only
* address fault. For system mode, if the access is valid, call
* tlb_set_page and return true; if the access is invalid, and
@@ -204,8 +208,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- void (*synchronize_from_tb)(CPUState *cpu,
- const struct TranslationBlock *tb);
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 5628a156d1..12b6a91d62 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -213,8 +213,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
TARGET_FMT_lx "] %s\n",
last_tb->tc.ptr, last_tb->pc,
lookup_symbol(last_tb->pc));
- if (cc->synchronize_from_tb) {
- cc->synchronize_from_tb(cpu, last_tb);
+ if (cc->tcg_ops.synchronize_from_tb) {
+ cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
} else {
assert(cc->set_pc);
cc->set_pc(cpu, last_tb->pc);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fa4d4ba4eb..140cb33f07 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+#ifdef CONFIG_TCG
static void arm_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -70,6 +71,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs,
env->regs[15] = tb->pc;
}
}
+#endif /* CONFIG_TCG */
static bool arm_cpu_has_work(CPUState *cs)
{
@@ -2257,7 +2259,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
- cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
@@ -2277,6 +2278,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = arm_translate_init;
+ cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index fb66695fbb..a82fa9d7a8 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -208,7 +208,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_ops.initialize = avr_cpu_tcg_init;
- cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
cc->gdb_num_core_regs = 35;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 80e3081631..94ea3014a3 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -144,7 +144,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
- cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
cc->tlb_fill = hppa_cpu_tlb_fill;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index d90502a0cc..874286de28 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -61,7 +61,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
{
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
- cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f2978ca726..e40d1db88d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -369,7 +369,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
- cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tlb_fill = mb_cpu_tlb_fill;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b96c3d5969..350f1c66c7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -257,6 +257,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+#ifdef CONFIG_TCG
static void mips_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -267,6 +268,7 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs,
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
+#endif /* CONFIG_TCG */
static bool mips_cpu_has_work(CPUState *cs)
{
@@ -678,7 +680,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
- cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
@@ -690,6 +691,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 60d0b43153..1e9bd3c313 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -597,7 +597,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
- cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 33;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index cdcab49c8a..4e0de14eef 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -190,7 +190,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
- cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index b86753cda5..130debe074 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,7 +223,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
- cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
cc->tlb_fill = superh_cpu_tlb_fill;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 3ab71e9d00..0ae38eb496 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -870,7 +870,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
#endif
cc->set_pc = sparc_cpu_set_pc;
- cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tlb_fill = sparc_cpu_tlb_fill;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index bf135af40f..09cc6a0e62 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -162,7 +162,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops
2021-01-28 9:27 ` [PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops Claudio Fontana
@ 2021-01-28 18:58 ` Alex Bennée
2021-01-28 23:01 ` Richard Henderson
0 siblings, 1 reply; 44+ messages in thread
From: Alex Bennée @ 2021-01-28 18:58 UTC (permalink / raw)
To: Claudio Fontana
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Richard Henderson, qemu-devel, Roman Bolshakov, Alistair Francis,
Paolo Bonzini, Philippe Mathieu-Daudé
Claudio Fontana <cfontana@suse.de> writes:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>
> [claudio: wrapped in CONFIG_TCG]
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> ---
> include/hw/core/cpu.h | 20 +++++++++++---------
> accel/tcg/cpu-exec.c | 4 ++--
> target/arm/cpu.c | 4 +++-
> target/avr/cpu.c | 2 +-
> target/hppa/cpu.c | 2 +-
> target/i386/tcg/tcg-cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 4 +++-
> target/riscv/cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/tricore/cpu.c | 2 +-
> 13 files changed, 28 insertions(+), 22 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 96fdca39d2..b3c1bb77eb 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -87,6 +87,17 @@ typedef struct TcgCpuOperations {
> * Called when the first CPU is realized.
> */
> void (*initialize)(void);
> + /**
> + * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
> + *
> + * This is called when we abandon execution of a TB before
> + * starting it, and must set all parts of the CPU state which
> + * the previous TB in the chain may not have updated. This
> + * will need to do more. If this hook is not implemented then
> + * the default is to call @set_pc(tb->pc).
> + */
Possibly re-word a little more?
...TB in the chain may not have updated. By default when no hook is
defined a call is made to @set_pc(tb->pc). If more state needs to be
restored the front-end must provide a hook function and restore all the
state there.
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index fa4d4ba4eb..140cb33f07 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
> }
> }
>
> +#ifdef CONFIG_TCG
> static void arm_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> @@ -70,6 +71,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs,
> env->regs[15] = tb->pc;
> }
> }
> +#endif /* CONFIG_TCG */
Looking at the function here I wonder if we should be worried about the
thumb state? Peter?
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
if (is_a64(env)) {
env->pc = value;
env->thumb = 0;
} else {
env->regs[15] = value & ~1;
env->thumb = value & 1;
}
}
#ifdef CONFIG_TCG
void arm_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
/*
* It's OK to look at env for the current mode here, because it's
* never possible for an AArch64 TB to chain to an AArch32 TB.
*/
if (is_a64(env)) {
env->pc = tb->pc;
} else {
env->regs[15] = tb->pc;
}
}
#endif /* CONFIG_TCG */
Otherwise:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops
2021-01-28 18:58 ` Alex Bennée
@ 2021-01-28 23:01 ` Richard Henderson
0 siblings, 0 replies; 44+ messages in thread
From: Richard Henderson @ 2021-01-28 23:01 UTC (permalink / raw)
To: Alex Bennée, Claudio Fontana
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
qemu-devel, Roman Bolshakov, Alistair Francis, Paolo Bonzini,
Philippe Mathieu-Daudé
On 1/28/21 8:58 AM, Alex Bennée wrote:
> Looking at the function here I wonder if we should be worried about the
> thumb state? Peter?
>
> static void arm_cpu_set_pc(CPUState *cs, vaddr value)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
>
> if (is_a64(env)) {
> env->pc = value;
> env->thumb = 0;
> } else {
> env->regs[15] = value & ~1;
> env->thumb = value & 1;
> }
> }
Plausible. You could possibly test this via gdbstub, as there are not many
other users. I think it would be of the form:
(gdb) call foo()
where foo is a thumb function.
> #ifdef CONFIG_TCG
> void arm_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
>
> /*
> * It's OK to look at env for the current mode here, because it's
> * never possible for an AArch64 TB to chain to an AArch32 TB.
> */
> if (is_a64(env)) {
> env->pc = tb->pc;
> } else {
> env->regs[15] = tb->pc;
> }
> }
> #endif /* CONFIG_TCG */
This function need only handle any state that is "deferred" across goto_tb.
This is almost always simply the pc, e.g.
if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n);
gen_set_pc_im(s, dest);
tcg_gen_exit_tb(s->base.tb, n);
A few targets do a bit more than that, especially vs delayed branches, but ARM
does not.
But there should be no thumb state that ought to be updated here.
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v14 05/22] cpu: Move cpu_exec_* to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (3 preceding siblings ...)
2021-01-28 9:27 ` [PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops Claudio Fontana
@ 2021-01-28 9:27 ` Claudio Fontana
2021-01-28 9:27 ` [PATCH v14 06/22] cpu: Move tlb_fill " Claudio Fontana
` (17 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:27 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 12 ++++++------
accel/tcg/cpu-exec.c | 12 ++++++------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/arm/cpu64.c | 5 ++++-
target/arm/cpu_tcg.c | 7 ++++++-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 6 +++---
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 16 ++++++++++------
25 files changed, 54 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b3c1bb77eb..eacefe28c7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -98,6 +98,12 @@ typedef struct TcgCpuOperations {
*/
void (*synchronize_from_tb)(CPUState *cpu,
const struct TranslationBlock *tb);
+ /** @cpu_exec_enter: Callback for cpu_exec preparation */
+ void (*cpu_exec_enter)(CPUState *cpu);
+ /** @cpu_exec_exit: Callback for cpu_exec cleanup */
+ void (*cpu_exec_exit)(CPUState *cpu);
+ /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
+ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
} TcgCpuOperations;
#endif /* CONFIG_TCG */
@@ -168,9 +174,6 @@ typedef struct TcgCpuOperations {
* @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
* gdb stub. Returns a pointer to the XML contents for the specified XML file
* or NULL if the CPU doesn't have a dynamically generated content for it.
- * @cpu_exec_enter: Callback for cpu_exec preparation.
- * @cpu_exec_exit: Callback for cpu_exec cleanup.
- * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
* @disas_set_info: Setup architecture specific components of disassembly info
* @adjust_watchpoint_address: Perform a target-specific adjustment to an
* address before attempting to match it against watchpoints.
@@ -233,9 +236,6 @@ struct CPUClass {
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
- void (*cpu_exec_enter)(CPUState *cpu);
- void (*cpu_exec_exit)(CPUState *cpu);
- bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 12b6a91d62..953f050698 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -262,8 +262,8 @@ static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->cpu_exec_enter) {
- cc->cpu_exec_enter(cpu);
+ if (cc->tcg_ops.cpu_exec_enter) {
+ cc->tcg_ops.cpu_exec_enter(cpu);
}
}
@@ -271,8 +271,8 @@ static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->cpu_exec_exit) {
- cc->cpu_exec_exit(cpu);
+ if (cc->tcg_ops.cpu_exec_exit) {
+ cc->tcg_ops.cpu_exec_exit(cpu);
}
}
@@ -655,8 +655,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
- if (cc->cpu_exec_interrupt &&
- cc->cpu_exec_interrupt(cpu, interrupt_request)) {
+ if (cc->tcg_ops.cpu_exec_interrupt &&
+ cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index d66f0351a9..d9ced1635a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -218,7 +218,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
cc->do_interrupt = alpha_cpu_do_interrupt;
- cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 140cb33f07..98a5a0c648 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2256,7 +2256,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
cc->gdb_read_register = arm_cpu_gdb_read_register;
@@ -2278,6 +2277,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = arm_translate_init;
+ cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c5..a9a1cdb871 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -805,7 +805,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
+#endif /* CONFIG_TCG */
+
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 98544db2df..f2e565166e 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -15,6 +15,7 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+#ifdef CONFIG_TCG
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
+#endif /* CONFIG_TCG */
static void arm926_initfn(Object *obj)
{
@@ -668,7 +670,10 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
#endif
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+#endif /* CONFIG_TCG */
+
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a82fa9d7a8..499a98dcee 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -199,7 +199,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = avr_cpu_has_work;
cc->do_interrupt = avr_cpu_do_interrupt;
- cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 4328f8e6c9..7489fc20c8 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -269,7 +269,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
cc->do_interrupt = cris_cpu_do_interrupt;
- cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 94ea3014a3..34c598230e 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -141,7 +141,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
cc->do_interrupt = hppa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 874286de28..b7c485aa76 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -60,10 +60,10 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
void tcg_cpu_common_class_init(CPUClass *cc)
{
cc->do_interrupt = x86_cpu_do_interrupt;
- cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
- cc->cpu_exec_enter = x86_cpu_exec_enter;
- cc->cpu_exec_exit = x86_cpu_exec_exit;
+ cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
+ cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index ef795b81a4..eea2d3e515 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -223,7 +223,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
cc->do_interrupt = lm32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 3604ece49b..0d5f8e0dd8 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -466,7 +466,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
cc->do_interrupt = m68k_cpu_do_interrupt;
- cc->cpu_exec_interrupt = m68k_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index e40d1db88d..35b4b2eb9d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -366,7 +366,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = mb_cpu_has_work;
cc->do_interrupt = mb_cpu_do_interrupt;
cc->do_unaligned_access = mb_cpu_do_unaligned_access;
- cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 350f1c66c7..929f98a57a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -677,7 +677,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
- cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->gdb_read_register = mips_cpu_gdb_read_register;
@@ -691,6 +690,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index c28eb05ef0..b0d51f77f5 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -222,7 +222,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
cc->do_interrupt = nios2_cpu_do_interrupt;
- cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index a957f59e2e..48c416e138 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -187,7 +187,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
cc->do_interrupt = openrisc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e9bd3c313..81ec7e6c99 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -594,7 +594,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
cc->do_interrupt = riscv_cpu_do_interrupt;
- cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 4e0de14eef..9493e9031a 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -187,7 +187,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
cc->do_interrupt = rx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 890781e74c..53c2f6f89e 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -508,7 +508,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
- cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 130debe074..b2d4e3648c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -220,7 +220,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
cc->do_interrupt = superh_cpu_do_interrupt;
- cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 0ae38eb496..139939494e 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -864,7 +864,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index cd24d0eb9d..4c6176d26e 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -148,7 +148,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
cc->do_interrupt = tilegx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
cc->tlb_fill = tilegx_cpu_tlb_fill;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 226bf4226e..84c3419989 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -132,7 +132,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
cc->do_interrupt = uc32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->tlb_fill = uc32_cpu_tlb_fill;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 5a6f5bf88b..42a5e4ebe8 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -195,7 +195,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
cc->do_interrupt = xtensa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 189f27cd1c..2b0343686f 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10700,6 +10700,7 @@ static void ppc_cpu_reset(DeviceState *dev)
}
#ifndef CONFIG_USER_ONLY
+
static bool ppc_cpu_is_big_endian(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -10710,6 +10711,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
return !msr_le;
}
+#ifdef CONFIG_TCG
static void ppc_cpu_exec_enter(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -10731,7 +10733,9 @@ static void ppc_cpu_exec_exit(CPUState *cs)
vhc->cpu_exec_exit(cpu->vhyp, cpu);
}
}
-#endif
+#endif /* CONFIG_TCG */
+
+#endif /* !CONFIG_USER_ONLY */
static void ppc_cpu_instance_init(Object *obj)
{
@@ -10842,7 +10846,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = ppc_cpu_class_by_name;
cc->has_work = ppc_cpu_has_work;
cc->do_interrupt = ppc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
@@ -10879,12 +10882,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#endif
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
+ cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
cc->tlb_fill = ppc_cpu_tlb_fill;
-#endif
#ifndef CONFIG_USER_ONLY
- cc->cpu_exec_enter = ppc_cpu_exec_enter;
- cc->cpu_exec_exit = ppc_cpu_exec_exit;
-#endif
+ cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
+ cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
+#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
cc->disas_set_info = ppc_disas_set_info;
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 06/22] cpu: Move tlb_fill to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (4 preceding siblings ...)
2021-01-28 9:27 ` [PATCH v14 05/22] cpu: Move cpu_exec_* " Claudio Fontana
@ 2021-01-28 9:27 ` Claudio Fontana
2021-01-28 9:27 ` [PATCH v14 07/22] cpu: Move debug_excp_handler " Claudio Fontana
` (16 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:27 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 21 ++++++++++++---------
accel/tcg/cputlb.c | 7 ++++---
accel/tcg/user-exec.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
26 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index eacefe28c7..aa464c9633 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -104,6 +104,18 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /**
+ * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
+ *
+ * For system mode, if the access is valid, call tlb_set_page
+ * and return true; if the access is invalid, and probe is
+ * true, return false; otherwise raise an exception and do
+ * not return. For user-only mode, always raise an exception
+ * and do not return.
+ */
+ bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
} TcgCpuOperations;
#endif /* CONFIG_TCG */
@@ -138,12 +150,6 @@ typedef struct TcgCpuOperations {
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
- * address fault. For system mode, if the access is valid, call
- * tlb_set_page and return true; if the access is invalid, and
- * probe is true, return false; otherwise raise an exception and
- * do not return. For user-only mode, always raise an exception
- * and do not return.
* @get_phys_page_debug: Callback for obtaining a physical address.
* @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
* associated memory transaction attributes to use for the access.
@@ -211,9 +217,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 7a69726ba4..b7717803b8 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1305,7 +1305,8 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
* This is not a probe, so only valid return is success; failure
* should result in exception + longjmp to the cpu loop.
*/
- ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
+ ok = cc->tcg_ops.tlb_fill(cpu, addr, size,
+ access_type, mmu_idx, false, retaddr);
assert(ok);
}
@@ -1576,8 +1577,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
CPUState *cs = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cs);
- if (!cc->tlb_fill(cs, addr, fault_size, access_type,
- mmu_idx, nonfault, retaddr)) {
+ if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
+ mmu_idx, nonfault, retaddr)) {
/* Non-faulting page table read failed. */
*phost = NULL;
return TLB_INVALID_MASK;
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 1215b55ca0..5509dd53e9 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -187,7 +187,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
- cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
+ cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
@@ -217,8 +217,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
} else {
CPUState *cpu = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tlb_fill(cpu, addr, fault_size, access_type,
- MMU_USER_IDX, false, ra);
+ cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type,
+ MMU_USER_IDX, false, ra);
g_assert_not_reached();
}
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index d9ced1635a..9f36f824fd 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -223,7 +223,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
- cc->tlb_fill = alpha_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 98a5a0c648..27a16c1950 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2279,7 +2279,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.initialize = arm_translate_init;
cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
- cc->tlb_fill = arm_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 499a98dcee..d6e93049b4 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -204,7 +204,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->tlb_fill = avr_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_ops.initialize = avr_cpu_tcg_init;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 7489fc20c8..9222717f3e 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -274,7 +274,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
- cc->tlb_fill = cris_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 34c598230e..d5a25014e8 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -147,7 +147,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
- cc->tlb_fill = hppa_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index b7c485aa76..85b69224a9 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -65,7 +65,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
- cc->tlb_fill = x86_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
#endif
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index eea2d3e515..76dc728858 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -228,7 +228,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
- cc->tlb_fill = lm32_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = lm32_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 0d5f8e0dd8..e38e4d5456 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -471,7 +471,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
- cc->tlb_fill = m68k_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
cc->do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 35b4b2eb9d..3c09507069 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -372,7 +372,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
- cc->tlb_fill = mb_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 929f98a57a..63c0f3b94c 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -692,7 +692,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.initialize = mips_tcg_init;
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
- cc->tlb_fill = mips_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#endif
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 224cfc8361..1177d092c1 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -110,7 +110,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
- cc->tlb_fill = moxie_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index b0d51f77f5..1384836de0 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -226,7 +226,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
- cc->tlb_fill = nios2_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 48c416e138..9857bfde23 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -192,7 +192,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
- cc->tlb_fill = openrisc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = openrisc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 81ec7e6c99..9d813924ef 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,7 +618,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
cc->tcg_ops.initialize = riscv_translate_init;
- cc->tlb_fill = riscv_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill;
device_class_set_props(dc, riscv_cpu_properties);
}
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 9493e9031a..77609728b8 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -196,7 +196,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->tcg_ops.initialize = rx_translate_init;
- cc->tlb_fill = rx_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "rx-core.xml";
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 53c2f6f89e..ceee62ddca 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -516,7 +516,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = s390_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = s390x_translate_init;
- cc->tlb_fill = s390_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = s390_cpu_tlb_fill;
#endif
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index b2d4e3648c..1f6c687c3c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -226,7 +226,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
- cc->tlb_fill = superh_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 139939494e..19e90a414d 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -873,7 +873,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
- cc->tlb_fill = sparc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 4c6176d26e..75b3a4bae3 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -151,7 +151,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
- cc->tlb_fill = tilegx_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
cc->tcg_ops.initialize = tilegx_tcg_init;
}
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 09cc6a0e62..9b21b640e2 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -165,7 +165,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = tricore_tcg_init;
- cc->tlb_fill = tricore_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = tricore_cpu_tlb_fill;
}
#define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 84c3419989..a57d315d2f 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -135,7 +135,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->tlb_fill = uc32_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 42a5e4ebe8..e764dbeb73 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -201,7 +201,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
- cc->tlb_fill = xtensa_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 2b0343686f..1e0fc5ac3d 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10883,7 +10883,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
- cc->tlb_fill = ppc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 07/22] cpu: Move debug_excp_handler to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (5 preceding siblings ...)
2021-01-28 9:27 ` [PATCH v14 06/22] cpu: Move tlb_fill " Claudio Fontana
@ 2021-01-28 9:27 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 08/22] target/arm: do not use cc->do_interrupt for KVM directly Claudio Fontana
` (15 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:27 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index aa464c9633..a0e040c617 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -116,6 +116,8 @@ typedef struct TcgCpuOperations {
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+ /** @debug_excp_handler: Callback for handling debug exceptions */
+ void (*debug_excp_handler)(CPUState *cpu);
} TcgCpuOperations;
#endif /* CONFIG_TCG */
@@ -161,7 +163,6 @@ typedef struct TcgCpuOperations {
* @gdb_write_register: Callback for letting GDB write a register.
* @debug_check_watchpoint: Callback: return true if the architectural
* watchpoint whose address has matched should really fire.
- * @debug_excp_handler: Callback for handling debug exceptions.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
@@ -224,7 +225,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
- void (*debug_excp_handler)(CPUState *cpu);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 953f050698..e7e54fd75d 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -512,8 +512,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
- if (cc->debug_excp_handler) {
- cc->debug_excp_handler(cpu);
+ if (cc->tcg_ops.debug_excp_handler) {
+ cc->tcg_ops.debug_excp_handler(cpu);
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 27a16c1950..66ac210b0c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2280,7 +2280,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
- cc->debug_excp_handler = arm_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 85b69224a9..6c1ebbdcc6 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -67,6 +67,6 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->tcg_ops.initialize = tcg_x86_init;
cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->debug_excp_handler = breakpoint_handler;
+ cc->tcg_ops.debug_excp_handler = breakpoint_handler;
#endif
}
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 76dc728858..bbe1405e32 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -235,7 +235,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
- cc->debug_excp_handler = lm32_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
cc->tcg_ops.initialize = lm32_translate_init;
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index ceee62ddca..8ade66178e 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -509,7 +509,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
- cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e764dbeb73..b6f13ceb32 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -207,7 +207,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
- cc->debug_excp_handler = xtensa_breakpoint_handler;
+ cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 08/22] target/arm: do not use cc->do_interrupt for KVM directly
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (6 preceding siblings ...)
2021-01-28 9:27 ` [PATCH v14 07/22] cpu: Move debug_excp_handler " Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 09/22] cpu: move cc->do_interrupt to tcg_ops Claudio Fontana
` (14 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture state in a
similar way where userspace code has identified that it needs to
deliver an exception to the guest.
In the case of ARM, that includes:
1) the vcpu thread got a SIGBUS indicating a memory error,
and we need to deliver a Synchronous External Abort to the guest to
let it know about the error.
2) the kernel told us about a debug exception (breakpoint, watchpoint)
but it is not for one of QEMU's own gdbstub breakpoints/watchpoints
so it must be a breakpoint the guest itself has set up, therefore
we need to deliver it to the guest.
So in order to reuse code, the same arm_do_interrupt function is used.
This is all fine, but we need to avoid calling it using the callback
registered in CPUClass, since that one is now TCG-only.
Fortunately this is easily solved by replacing calls to
CPUClass::do_interrupt() with explicit calls to arm_do_interrupt().
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 4 ++++
target/arm/kvm64.c | 6 ++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2ead3fcbd..e42b94ce96 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9960,6 +9960,10 @@ static void handle_semihosting(CPUState *cs)
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
+ *
+ * Note: this is used for both TCG (as the do_interrupt tcg op),
+ * and KVM to re-inject guest debug exceptions, and to
+ * inject a Synchronous-External-Abort.
*/
void arm_cpu_do_interrupt(CPUState *cs)
{
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index f74bac2457..3728b3a336 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -944,7 +944,6 @@ static void kvm_inject_arm_sea(CPUState *c)
{
ARMCPU *cpu = ARM_CPU(c);
CPUARMState *env = &cpu->env;
- CPUClass *cc = CPU_GET_CLASS(c);
uint32_t esr;
bool same_el;
@@ -960,7 +959,7 @@ static void kvm_inject_arm_sea(CPUState *c)
env->exception.syndrome = esr;
- cc->do_interrupt(c);
+ arm_cpu_do_interrupt(c);
}
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
@@ -1491,7 +1490,6 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
{
int hsr_ec = syn_get_ec(debug_exit->hsr);
ARMCPU *cpu = ARM_CPU(cs);
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUARMState *env = &cpu->env;
/* Ensure PC is synchronised */
@@ -1545,7 +1543,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
env->exception.vaddress = debug_exit->far;
env->exception.target_el = 1;
qemu_mutex_lock_iothread();
- cc->do_interrupt(cs);
+ arm_cpu_do_interrupt(cs);
qemu_mutex_unlock_iothread();
return false;
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 09/22] cpu: move cc->do_interrupt to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (7 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 08/22] target/arm: do not use cc->do_interrupt for KVM directly Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 10/22] cpu: move cc->transaction_failed " Claudio Fontana
` (13 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c | 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/arm/cpu_tcg.c | 9 ++++-----
target/avr/cpu.c | 2 +-
target/avr/helper.c | 4 ++--
target/cris/cpu.c | 12 ++++++------
target/cris/helper.c | 4 ++--
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 ++--
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
27 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index a0e040c617..8fcdd55494 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -104,6 +104,8 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /** @do_interrupt: Callback for interrupt handling. */
+ void (*do_interrupt)(CPUState *cpu);
/**
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
*
@@ -129,7 +131,6 @@ typedef struct TcgCpuOperations {
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_interrupt: Callback for interrupt handling.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
* @do_transaction_failed: Callback for handling failed memory transactions
@@ -199,7 +200,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- void (*do_interrupt)(CPUState *cpu);
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index e7e54fd75d..633ee3ef9e 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -547,7 +547,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->do_interrupt(cpu);
+ cc->tcg_ops.do_interrupt(cpu);
#endif
*ret = cpu->exception_index;
cpu->exception_index = -1;
@@ -556,7 +556,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (replay_exception()) {
CPUClass *cc = CPU_GET_CLASS(cpu);
qemu_mutex_lock_iothread();
- cc->do_interrupt(cpu);
+ cc->tcg_ops.do_interrupt(cpu);
qemu_mutex_unlock_iothread();
cpu->exception_index = -1;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 9f36f824fd..66f1166672 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -217,7 +217,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
- cc->do_interrupt = alpha_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = alpha_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 66ac210b0c..dfb2398392 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -590,7 +590,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
return true;
}
@@ -2261,7 +2261,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_cpu_do_interrupt;
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->vmsd = &vmstate_arm_cpu;
@@ -2286,6 +2285,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#if !defined(CONFIG_USER_ONLY)
cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+ cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif
}
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index f2e565166e..d9c160f1ac 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -34,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
return ret;
@@ -666,12 +666,11 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = arm_v7m_cpu_do_interrupt;
#endif
-
-#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
#endif /* CONFIG_TCG */
cc->gdb_core_xml_file = "arm-m-profile.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index d6e93049b4..476e645b37 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -198,7 +198,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = avr_cpu_class_by_name;
cc->has_work = avr_cpu_has_work;
- cc->do_interrupt = avr_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = avr_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
diff --git a/target/avr/helper.c b/target/avr/helper.c
index d96d14372b..69d3b6181f 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -34,7 +34,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_RESET) {
if (cpu_interrupts_enabled(env)) {
cs->exception_index = EXCP_RESET;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
@@ -45,7 +45,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
int index = ctz32(env->intsrc);
cs->exception_index = EXCP_INT(index);
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
env->intsrc &= env->intsrc - 1; /* clear the interrupt */
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 9222717f3e..b65743e8ca 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -199,7 +199,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 8;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -210,7 +210,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -221,7 +221,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 10;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -232,7 +232,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 11;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -243,7 +243,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 17;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -268,7 +268,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
- cc->do_interrupt = cris_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = cris_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
diff --git a/target/cris/helper.c b/target/cris/helper.c
index ed45c3d9b7..1f4d6f7d45 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -299,7 +299,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
if (interrupt_request & CPU_INTERRUPT_NMI) {
@@ -311,7 +311,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
cs->exception_index = EXCP_NMI;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
}
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d5a25014e8..68233acf53 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -140,7 +140,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
- cc->do_interrupt = hppa_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = hppa_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 6c1ebbdcc6..4a53cd89e2 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -59,7 +59,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
void tcg_cpu_common_class_init(CPUClass *cc)
{
- cc->do_interrupt = x86_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = x86_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index bbe1405e32..fb3761b749 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -222,7 +222,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
- cc->do_interrupt = lm32_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = lm32_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index e38e4d5456..69093a621f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -465,7 +465,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
- cc->do_interrupt = m68k_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = m68k_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 3c09507069..c93e44b8e5 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -364,7 +364,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
- cc->do_interrupt = mb_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
cc->do_unaligned_access = mb_cpu_do_unaligned_access;
cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 63c0f3b94c..a88a138a8d 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -676,7 +676,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
- cc->do_interrupt = mips_cpu_do_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->gdb_read_register = mips_cpu_gdb_read_register;
@@ -690,10 +689,11 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
-#endif
+#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 1177d092c1..36bef4d357 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -107,7 +107,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = moxie_cpu_class_by_name;
cc->has_work = moxie_cpu_has_work;
- cc->do_interrupt = moxie_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 1384836de0..b5fe779ceb 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -221,7 +221,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
- cc->do_interrupt = nios2_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = nios2_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 9857bfde23..1a31f7564f 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -186,7 +186,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
- cc->do_interrupt = openrisc_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = openrisc_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9d813924ef..345b78fc3d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -593,7 +593,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
- cc->do_interrupt = riscv_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = riscv_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 77609728b8..e79f009cbd 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -186,7 +186,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
- cc->do_interrupt = rx_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = rx_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 8ade66178e..e6cf933594 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -496,7 +496,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = s390_cpu_class_by_name,
cc->has_work = s390_cpu_has_work;
#ifdef CONFIG_TCG
- cc->do_interrupt = s390_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = s390_cpu_do_interrupt;
#endif
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 1f6c687c3c..f69360fc16 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -219,7 +219,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
- cc->do_interrupt = superh_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = superh_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 19e90a414d..871b2a83c6 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -863,7 +863,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
- cc->do_interrupt = sparc_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = sparc_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 75b3a4bae3..7d4ead4ef1 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -147,7 +147,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
- cc->do_interrupt = tilegx_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = tilegx_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index a57d315d2f..e27ffc571a 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -131,7 +131,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
- cc->do_interrupt = uc32_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = uc32_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index b6f13ceb32..3ff025f0fe 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -194,7 +194,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
- cc->do_interrupt = xtensa_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = xtensa_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 1e0fc5ac3d..b16430a9d4 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,7 +10845,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = ppc_cpu_class_by_name;
cc->has_work = ppc_cpu_has_work;
- cc->do_interrupt = ppc_cpu_do_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
@@ -10883,6 +10882,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
+ cc->tcg_ops.do_interrupt = ppc_cpu_do_interrupt;
cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 10/22] cpu: move cc->transaction_failed to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (8 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 09/22] cpu: move cc->do_interrupt to tcg_ops Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 11/22] cpu: move do_unaligned_access " Claudio Fontana
` (12 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: replaced !CONFIG_USER_ONLY with CONFIG_SOFTMMU in cpu.h]
this is working around a dangerous issue of different parts of the code
seeing the struct TcgCpuOperations as different, because common_ss
sources never see target configuration macros like CONFIG_USER_ONLY.
We will keep conditional parts of the struct at the end,
so that no other fields' starting addresses can be screwed up by
different views of the struct.
This will be further improved in a later patch, where we change
the CPUClass struct member into a forward declared pointer.
code in hw/core/cpu.c and include/hw/core/cpu.h, as well as
other code outside of target, in headers, contains other uses of
CONFIG_USER_ONLY, and they are potential issues.
CONFIG_USER_ONLY should be poisoned, and in general one must be
always wary of using CONFIG_ macros in common_ss code.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/core/cpu.h | 32 ++++++++++++++++++++++----------
hw/mips/jazz.c | 9 +++++++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c | 4 ++--
12 files changed, 43 insertions(+), 24 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8fcdd55494..fbd8a9e5c7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -121,6 +121,20 @@ typedef struct TcgCpuOperations {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+#ifdef NEED_CPU_H
+#ifdef CONFIG_SOFTMMU
+ /**
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
+ */
+ void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+
+#endif /* CONFIG_SOFTMMU */
+#endif /* NEED_CPU_H */
+
} TcgCpuOperations;
#endif /* CONFIG_TCG */
@@ -133,8 +147,6 @@ typedef struct TcgCpuOperations {
* @has_work: Callback for checking if there is work to do.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -203,10 +215,6 @@ struct CPUClass {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
- void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -893,6 +901,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
}
+#ifdef CONFIG_TCG
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -902,12 +911,15 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
- cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
- mmu_idx, attrs, response, retaddr);
+ if (!cpu->ignore_memory_transaction_failures &&
+ cc->tcg_ops.do_transaction_failed) {
+ cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
+ access_type, mmu_idx, attrs,
+ response, retaddr);
}
}
-#endif
+#endif /* CONFIG_TCG */
+#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index f9442731dd..46c71a0ac8 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -116,6 +116,8 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE \
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
+
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -137,6 +139,7 @@ static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
mmu_idx, attrs, response, retaddr);
}
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
@@ -205,8 +208,10 @@ static void mips_jazz_init(MachineState *machine,
* memory region that catches all memory accesses, as we do on Malta.
*/
cc = CPU_GET_CLASS(cpu);
- real_do_transaction_failed = cc->do_transaction_failed;
- cc->do_transaction_failed = mips_jazz_do_transaction_failed;
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
+ real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
/* allocate RAM */
memory_region_add_subregion(address_space, 0, machine->ram);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 66f1166672..a1696bebeb 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -225,7 +225,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index dfb2398392..bd1882944c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2283,11 +2283,11 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
- cc->do_transaction_failed = arm_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
-#endif
+#endif /* CONFIG_TCG */
}
#ifdef CONFIG_KVM
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 69093a621f..e68b933c84 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -473,7 +473,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
- cc->do_transaction_failed = m68k_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
#endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index c93e44b8e5..e405f6422d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -374,7 +374,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mb_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a88a138a8d..ed2a7664e9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -681,7 +681,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mips_cpu_do_transaction_failed;
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
@@ -693,6 +692,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
+ cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 345b78fc3d..9a23af9a9d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -609,7 +609,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f8350f5f78..2f43939fb6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -671,7 +671,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 871b2a83c6..8d6d7c1f83 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -875,7 +875,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 3ff025f0fe..fc52fde696 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -205,7 +205,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
- cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 05e2b7f70a..eeffee297d 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -261,7 +261,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cpu_loop_exit_restore(cs, retaddr);
}
-#else
+#else /* !CONFIG_USER_ONLY */
void xtensa_cpu_do_unaligned_access(CPUState *cs,
vaddr addr, MMUAccessType access_type,
@@ -337,4 +337,4 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall)
qemu_cpu_kick(cpu);
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 11/22] cpu: move do_unaligned_access to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (9 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 10/22] cpu: move cc->transaction_failed " Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 12/22] physmem: make watchpoint checking code TCG-only Claudio Fontana
` (11 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 22 +++++++++-------------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/hppa/cpu.c | 4 +++-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 3 ++-
target/nios2/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/s390x/excp_helper.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
14 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fbd8a9e5c7..95ff2c9eb0 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -131,7 +131,12 @@ typedef struct TcgCpuOperations {
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
-
+ /**
+ * @do_unaligned_access: Callback for unaligned access handling
+ */
+ void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
@@ -145,8 +150,6 @@ typedef struct TcgCpuOperations {
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_unaligned_access: Callback for unaligned access handling, if
- * the target defines #TARGET_ALIGNED_ONLY.
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -212,9 +215,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -890,18 +890,16 @@ CPUState *cpu_by_arch_id(int64_t id);
void cpu_interrupt(CPUState *cpu, int mask);
#ifdef NEED_CPU_H
-
-#ifdef CONFIG_SOFTMMU
+#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+ cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
}
-#ifdef CONFIG_TCG
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -918,9 +916,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
response, retaddr);
}
}
-#endif /* CONFIG_TCG */
-#endif /* CONFIG_SOFTMMU */
-
+#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
#endif /* NEED_CPU_H */
/**
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index a1696bebeb..0710298e5a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -226,7 +226,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
- cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index bd1882944c..aa264eec0a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2281,9 +2281,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
- cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 68233acf53..fd7f849a1c 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -71,6 +71,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
info->print_insn = print_insn_hppa;
}
+#ifndef CONFIG_USER_ONLY
static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -87,6 +88,7 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
cpu_loop_exit_restore(cs, retaddr);
}
+#endif /* CONFIG_USER_ONLY */
static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
{
@@ -150,9 +152,9 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
+ cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access;
dc->vmsd = &vmstate_hppa_cpu;
#endif
- cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->tcg_ops.initialize = hppa_translate_init;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index e405f6422d..6678310f51 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -365,7 +365,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
- cc->do_unaligned_access = mb_cpu_do_unaligned_access;
cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
@@ -375,6 +374,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = mb_cpu_do_unaligned_access;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ed2a7664e9..1e93e295cc 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -681,7 +681,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
#endif
@@ -694,6 +693,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
+
#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index b5fe779ceb..c43aa3d4c4 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -228,7 +228,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9a23af9a9d..5e85fd58b6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -610,7 +610,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
- cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index e6cf933594..a723ede8d1 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -510,7 +510,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
- cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 9cf66d3690..ce16af394b 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -634,4 +634,4 @@ void HELPER(monitor_call)(CPUS390XState *env, uint64_t monitor_code,
}
}
-#endif /* CONFIG_USER_ONLY */
+#endif /* !CONFIG_USER_ONLY */
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index f69360fc16..292152b562 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -228,7 +228,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = superh_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 8d6d7c1f83..1b785f60df 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -876,7 +876,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
- cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index fc52fde696..4b6381569f 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -203,7 +203,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b16430a9d4..27ab243c6e 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10850,7 +10850,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = ppc_cpu_set_pc;
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
- cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
@@ -10887,6 +10886,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
+ cc->tcg_ops.do_unaligned_access = ppc_cpu_do_unaligned_access;
#endif /* !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 12/22] physmem: make watchpoint checking code TCG-only
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (10 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 11/22] cpu: move do_unaligned_access " Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 19:09 ` Alex Bennée
2021-01-28 9:28 ` [PATCH v14 13/22] cpu: move adjust_watchpoint_address to tcg_ops Claudio Fontana
` (10 subsequent siblings)
22 siblings, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
softmmu/physmem.c | 141 +++++++++++++++++++++++-----------------------
1 file changed, 72 insertions(+), 69 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index cdcd197656..ef94e32583 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -840,6 +840,7 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
}
}
+#ifdef CONFIG_TCG
/* Return true if this watchpoint address matches the specified
* access (ie the address range covered by the watchpoint overlaps
* partially or completely with the address range covered by the
@@ -873,6 +874,77 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
return ret;
}
+/* Generate a debug exception if a watchpoint has been hit. */
+void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
+ MemTxAttrs attrs, int flags, uintptr_t ra)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ CPUWatchpoint *wp;
+
+ assert(tcg_enabled());
+ if (cpu->watchpoint_hit) {
+ /*
+ * We re-entered the check after replacing the TB.
+ * Now raise the debug interrupt so that it will
+ * trigger after the current instruction.
+ */
+ qemu_mutex_lock_iothread();
+ cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
+ qemu_mutex_unlock_iothread();
+ return;
+ }
+
+ addr = cc->adjust_watchpoint_address(cpu, addr, len);
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
+ if (watchpoint_address_matches(wp, addr, len)
+ && (wp->flags & flags)) {
+ if (replay_running_debug()) {
+ /*
+ * Don't process the watchpoints when we are
+ * in a reverse debugging operation.
+ */
+ replay_breakpoint();
+ return;
+ }
+ if (flags == BP_MEM_READ) {
+ wp->flags |= BP_WATCHPOINT_HIT_READ;
+ } else {
+ wp->flags |= BP_WATCHPOINT_HIT_WRITE;
+ }
+ wp->hitaddr = MAX(addr, wp->vaddr);
+ wp->hitattrs = attrs;
+ if (!cpu->watchpoint_hit) {
+ if (wp->flags & BP_CPU &&
+ !cc->debug_check_watchpoint(cpu, wp)) {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ continue;
+ }
+ cpu->watchpoint_hit = wp;
+
+ mmap_lock();
+ tb_check_watchpoint(cpu, ra);
+ if (wp->flags & BP_STOP_BEFORE_ACCESS) {
+ cpu->exception_index = EXCP_DEBUG;
+ mmap_unlock();
+ cpu_loop_exit_restore(cpu, ra);
+ } else {
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | curr_cflags();
+ mmap_unlock();
+ if (ra) {
+ cpu_restore_state(cpu, ra, true);
+ }
+ cpu_loop_exit_noexc(cpu);
+ }
+ }
+ } else {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ }
+ }
+}
+
+#endif /* CONFIG_TCG */
+
/* Called from RCU critical section */
static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
{
@@ -2355,75 +2427,6 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr)
return block->offset + offset;
}
-/* Generate a debug exception if a watchpoint has been hit. */
-void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUWatchpoint *wp;
-
- assert(tcg_enabled());
- if (cpu->watchpoint_hit) {
- /*
- * We re-entered the check after replacing the TB.
- * Now raise the debug interrupt so that it will
- * trigger after the current instruction.
- */
- qemu_mutex_lock_iothread();
- cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
- qemu_mutex_unlock_iothread();
- return;
- }
-
- addr = cc->adjust_watchpoint_address(cpu, addr, len);
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- if (watchpoint_address_matches(wp, addr, len)
- && (wp->flags & flags)) {
- if (replay_running_debug()) {
- /*
- * Don't process the watchpoints when we are
- * in a reverse debugging operation.
- */
- replay_breakpoint();
- return;
- }
- if (flags == BP_MEM_READ) {
- wp->flags |= BP_WATCHPOINT_HIT_READ;
- } else {
- wp->flags |= BP_WATCHPOINT_HIT_WRITE;
- }
- wp->hitaddr = MAX(addr, wp->vaddr);
- wp->hitattrs = attrs;
- if (!cpu->watchpoint_hit) {
- if (wp->flags & BP_CPU &&
- !cc->debug_check_watchpoint(cpu, wp)) {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- continue;
- }
- cpu->watchpoint_hit = wp;
-
- mmap_lock();
- tb_check_watchpoint(cpu, ra);
- if (wp->flags & BP_STOP_BEFORE_ACCESS) {
- cpu->exception_index = EXCP_DEBUG;
- mmap_unlock();
- cpu_loop_exit_restore(cpu, ra);
- } else {
- /* Force execution of one insn next time. */
- cpu->cflags_next_tb = 1 | curr_cflags();
- mmap_unlock();
- if (ra) {
- cpu_restore_state(cpu, ra, true);
- }
- cpu_loop_exit_noexc(cpu);
- }
- }
- } else {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- }
- }
-}
-
static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
MemTxAttrs attrs, void *buf, hwaddr len);
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v14 12/22] physmem: make watchpoint checking code TCG-only
2021-01-28 9:28 ` [PATCH v14 12/22] physmem: make watchpoint checking code TCG-only Claudio Fontana
@ 2021-01-28 19:09 ` Alex Bennée
0 siblings, 0 replies; 44+ messages in thread
From: Alex Bennée @ 2021-01-28 19:09 UTC (permalink / raw)
To: Claudio Fontana
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Richard Henderson, qemu-devel, Roman Bolshakov, Alistair Francis,
Paolo Bonzini, Philippe Mathieu-Daudé
Claudio Fontana <cfontana@suse.de> writes:
> cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v14 13/22] cpu: move adjust_watchpoint_address to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (11 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 12/22] physmem: make watchpoint checking code TCG-only Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 14/22] cpu: move debug_check_watchpoint " Claudio Fontana
` (9 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")
introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.
Make adjust_watchpoint_address optional and move it to tcg_ops.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/core/cpu.h | 7 ++++++-
hw/core/cpu.c | 6 ------
softmmu/physmem.c | 5 ++++-
target/arm/cpu.c | 2 +-
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 95ff2c9eb0..d6c6d32865 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -137,6 +137,12 @@ typedef struct TcgCpuOperations {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
+
+ /**
+ * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
+ */
+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
@@ -249,7 +255,6 @@ struct CPUClass {
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
- vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 57542b6906..3d5bf9fe02 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -383,11 +383,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu->cpu_index;
}
-static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
-{
- return addr;
-}
-
static Property cpu_common_props[] = {
#ifndef CONFIG_USER_ONLY
/* Create a memory property for softmmu CPU object,
@@ -421,7 +416,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
- k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index ef94e32583..c5cf9b839e 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -894,7 +894,10 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
return;
}
- addr = cc->adjust_watchpoint_address(cpu, addr, len);
+ if (cc->tcg_ops.adjust_watchpoint_address) {
+ /* this is currently used only by ARM BE32 */
+ addr = cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len);
+ }
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (watchpoint_address_matches(wp, addr, len)
&& (wp->flags & flags)) {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index aa264eec0a..2a14431065 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2284,7 +2284,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
- cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+ cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 14/22] cpu: move debug_check_watchpoint to tcg_ops
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (12 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 13/22] cpu: move adjust_watchpoint_address to tcg_ops Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Claudio Fontana
` (8 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.
Make debug_check_watchpoint optional, and move it to tcg_ops.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/core/cpu.h | 9 ++++++---
accel/tcg/user-exec.c | 3 ++-
hw/core/cpu.c | 9 ---------
softmmu/physmem.c | 4 ++--
target/arm/cpu.c | 4 ++--
5 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d6c6d32865..406e8a8606 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -143,6 +143,12 @@ typedef struct TcgCpuOperations {
*/
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+ /**
+ * @debug_check_watchpoint: return true if the architectural
+ * watchpoint whose address has matched should really fire, used by ARM
+ */
+ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
+
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
@@ -183,8 +189,6 @@ typedef struct TcgCpuOperations {
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @debug_check_watchpoint: Callback: return true if the architectural
- * watchpoint whose address has matched should really fire.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
@@ -238,7 +242,6 @@ struct CPUClass {
int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 5509dd53e9..9e6e188d19 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -187,7 +187,8 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
+ cc->tcg_ops.tlb_fill(cpu, address, 0, access_type,
+ MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 3d5bf9fe02..00330ba07d 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -186,14 +186,6 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
-{
- /* If no extra check is required, QEMU watchpoint match can be considered
- * as an architectural match.
- */
- return true;
-}
-
static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
{
return target_words_bigendian();
@@ -415,7 +407,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
- k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index c5cf9b839e..e85059f9c6 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -917,8 +917,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;
if (!cpu->watchpoint_hit) {
- if (wp->flags & BP_CPU &&
- !cc->debug_check_watchpoint(cpu, wp)) {
+ if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoint &&
+ !cc->tcg_ops.debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2a14431065..c9a66d3103 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2280,12 +2280,12 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
- cc->debug_check_watchpoint = arm_debug_check_watchpoint;
#if !defined(CONFIG_USER_ONLY)
+ cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
- cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
+ cc->tcg_ops.debug_check_watchpoint = arm_debug_check_watchpoint;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
}
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (13 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 14/22] cpu: move debug_check_watchpoint " Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-29 0:31 ` Richard Henderson
2021-01-28 9:28 ` [PATCH v14 16/22] accel: extend AccelState and AccelClass to user-mode Claudio Fontana
` (7 subsequent siblings)
22 siblings, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
this improves over the workaround in commit
("cpu: move cc->transaction_failed to tcg_ops")
by moving the tcg cpu operations into a separate file, which is
only included by target-specific code.
The context is that code in ss_common and ss_specific modules
might see different data structure layouts, due to missing
CONFIG_XXX in ss_common objects.
To be on the safe side, move over all details to tcg-cpu-ops.h,
which is to be included only by CONFIG_TCG target code,
and leave only a pointer in CPUClass, which for non-TCG is just
going to be NULL.
This also tidies up the code in all targets a bit, having all
tcg cpu operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/core/cpu.h | 122 ++++----------------------------
include/hw/core/tcg-cpu-ops.h | 95 +++++++++++++++++++++++++
target/arm/internals.h | 6 ++
accel/tcg/cpu-exec.c | 27 +++----
accel/tcg/cputlb.c | 35 +++++++--
accel/tcg/user-exec.c | 9 +--
hw/mips/jazz.c | 7 +-
softmmu/physmem.c | 13 ++--
target/alpha/cpu.c | 21 ++++--
target/arm/cpu.c | 45 ++++++++----
target/arm/cpu64.c | 7 +-
target/arm/cpu_tcg.c | 28 ++++++--
target/avr/cpu.c | 19 +++--
target/avr/helper.c | 5 +-
target/cris/cpu.c | 43 +++++++----
target/cris/helper.c | 5 +-
target/hppa/cpu.c | 22 ++++--
target/i386/tcg/tcg-cpu.c | 28 +++++---
target/lm32/cpu.c | 19 +++--
target/m68k/cpu.c | 19 +++--
target/microblaze/cpu.c | 25 +++++--
target/mips/cpu.c | 36 ++++++----
target/moxie/cpu.c | 15 +++-
target/nios2/cpu.c | 18 +++--
target/openrisc/cpu.c | 17 +++--
target/riscv/cpu.c | 23 ++++--
target/rx/cpu.c | 20 ++++--
target/s390x/cpu.c | 33 +++++----
target/sh4/cpu.c | 21 ++++--
target/sparc/cpu.c | 25 +++++--
target/tilegx/cpu.c | 17 +++--
target/tricore/cpu.c | 12 +++-
target/unicore32/cpu.c | 17 +++--
target/xtensa/cpu.c | 23 ++++--
target/ppc/translate_init.c.inc | 33 +++++----
MAINTAINERS | 1 +
36 files changed, 593 insertions(+), 318 deletions(-)
create mode 100644 include/hw/core/tcg-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 406e8a8606..500e2c4fce 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,84 +76,11 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
-#ifdef CONFIG_TCG
-/**
- * struct TcgCpuOperations: TCG operations specific to a CPU class
- */
-typedef struct TcgCpuOperations {
- /**
- * @initialize: Initalize TCG state
- *
- * Called when the first CPU is realized.
- */
- void (*initialize)(void);
- /**
- * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
- *
- * This is called when we abandon execution of a TB before
- * starting it, and must set all parts of the CPU state which
- * the previous TB in the chain may not have updated. This
- * will need to do more. If this hook is not implemented then
- * the default is to call @set_pc(tb->pc).
- */
- void (*synchronize_from_tb)(CPUState *cpu,
- const struct TranslationBlock *tb);
- /** @cpu_exec_enter: Callback for cpu_exec preparation */
- void (*cpu_exec_enter)(CPUState *cpu);
- /** @cpu_exec_exit: Callback for cpu_exec cleanup */
- void (*cpu_exec_exit)(CPUState *cpu);
- /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
- bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
- /** @do_interrupt: Callback for interrupt handling. */
- void (*do_interrupt)(CPUState *cpu);
- /**
- * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
- *
- * For system mode, if the access is valid, call tlb_set_page
- * and return true; if the access is invalid, and probe is
- * true, return false; otherwise raise an exception and do
- * not return. For user-only mode, always raise an exception
- * and do not return.
- */
- bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
- /** @debug_excp_handler: Callback for handling debug exceptions */
- void (*debug_excp_handler)(CPUState *cpu);
+/* see accel-cpu.h */
+struct AccelCPUClass;
-#ifdef NEED_CPU_H
-#ifdef CONFIG_SOFTMMU
- /**
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
- */
- void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
- /**
- * @do_unaligned_access: Callback for unaligned access handling
- */
- void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr);
-
- /**
- * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
- */
- vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
-
- /**
- * @debug_check_watchpoint: return true if the architectural
- * watchpoint whose address has matched should really fire, used by ARM
- */
- bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
-
-#endif /* CONFIG_SOFTMMU */
-#endif /* NEED_CPU_H */
-
-} TcgCpuOperations;
-#endif /* CONFIG_TCG */
+/* see tcg-cpu-ops.h */
+struct TCGCPUOps;
/**
* CPUClass:
@@ -264,9 +191,14 @@ struct CPUClass {
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
-#ifdef CONFIG_TCG
- TcgCpuOperations tcg_ops;
-#endif /* CONFIG_TCG */
+ /*
+ * NB: this should be covered by CONFIG_TCG, but it is unsafe to do it here,
+ * as this header is included by both ss_specific and ss_common code,
+ * leading to potential differences in the data structure between modules.
+ * We could always keep it last, but it seems safer to just leave this
+ * pointer NULL for non-TCG.
+ */
+ struct TCGCPUOps *tcg_ops;
};
/*
@@ -897,36 +829,6 @@ CPUState *cpu_by_arch_id(int64_t id);
void cpu_interrupt(CPUState *cpu, int mask);
-#ifdef NEED_CPU_H
-#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
-static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
-}
-
-static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response,
- uintptr_t retaddr)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cpu->ignore_memory_transaction_failures &&
- cc->tcg_ops.do_transaction_failed) {
- cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
- access_type, mmu_idx, attrs,
- response, retaddr);
- }
-}
-#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
-#endif /* NEED_CPU_H */
-
/**
* cpu_set_pc:
* @cpu: The CPU to set the program counter for.
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
new file mode 100644
index 0000000000..406ef56184
--- /dev/null
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -0,0 +1,95 @@
+/*
+ * TCG CPU-specific operations
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPU_OPS_H
+#define TCG_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+struct TCGCPUOps {
+ /**
+ * @initialize: Initalize TCG state
+ *
+ * Called when the first CPU is realized.
+ */
+ void (*initialize)(void);
+ /**
+ * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
+ *
+ * This is called when we abandon execution of a TB before
+ * starting it, and must set all parts of the CPU state which
+ * the previous TB in the chain may not have updated. This
+ * will need to do more. If this hook is not implemented then
+ * the default is to call @set_pc(tb->pc).
+ */
+ void (*synchronize_from_tb)(CPUState *cpu,
+ const struct TranslationBlock *tb);
+ /** @cpu_exec_enter: Callback for cpu_exec preparation */
+ void (*cpu_exec_enter)(CPUState *cpu);
+ /** @cpu_exec_exit: Callback for cpu_exec cleanup */
+ void (*cpu_exec_exit)(CPUState *cpu);
+ /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
+ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /**
+ * @do_interrupt: Callback for interrupt handling.
+ *
+ * note that this is in general SOFTMMU only, but it actually isn't
+ * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it
+ * in the SOFTMMU section in general.
+ */
+ void (*do_interrupt)(CPUState *cpu);
+ /**
+ * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
+ *
+ * For system mode, if the access is valid, call tlb_set_page
+ * and return true; if the access is invalid, and probe is
+ * true, return false; otherwise raise an exception and do
+ * not return. For user-only mode, always raise an exception
+ * and do not return.
+ */
+ bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+ /** @debug_excp_handler: Callback for handling debug exceptions */
+ void (*debug_excp_handler)(CPUState *cpu);
+
+#ifdef NEED_CPU_H
+#ifdef CONFIG_SOFTMMU
+ /**
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
+ */
+ void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+ /**
+ * @do_unaligned_access: Callback for unaligned access handling
+ */
+ void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
+
+ /**
+ * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
+ */
+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+
+ /**
+ * @debug_check_watchpoint: return true if the architectural
+ * watchpoint whose address has matched should really fire, used by ARM
+ */
+ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
+
+#endif /* CONFIG_SOFTMMU */
+#endif /* NEED_CPU_H */
+
+};
+
+#endif /* TCG_CPU_OPS_H */
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 853fa88fd6..448982dd2f 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -171,6 +171,12 @@ static inline int r14_bank_number(int mode)
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);
+#ifdef CONFIG_TCG
+void arm_cpu_synchronize_from_tb(CPUState *cs,
+ const struct TranslationBlock *tb);
+#endif /* CONFIG_TCG */
+
+
enum arm_fprounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 633ee3ef9e..d9ef69121c 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -21,6 +21,7 @@
#include "qemu-common.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "trace.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
@@ -213,8 +214,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
TARGET_FMT_lx "] %s\n",
last_tb->tc.ptr, last_tb->pc,
lookup_symbol(last_tb->pc));
- if (cc->tcg_ops.synchronize_from_tb) {
- cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
+ if (cc->tcg_ops->synchronize_from_tb) {
+ cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
} else {
assert(cc->set_pc);
cc->set_pc(cpu, last_tb->pc);
@@ -262,8 +263,8 @@ static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->tcg_ops.cpu_exec_enter) {
- cc->tcg_ops.cpu_exec_enter(cpu);
+ if (cc->tcg_ops->cpu_exec_enter) {
+ cc->tcg_ops->cpu_exec_enter(cpu);
}
}
@@ -271,8 +272,8 @@ static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->tcg_ops.cpu_exec_exit) {
- cc->tcg_ops.cpu_exec_exit(cpu);
+ if (cc->tcg_ops->cpu_exec_exit) {
+ cc->tcg_ops->cpu_exec_exit(cpu);
}
}
@@ -512,8 +513,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
- if (cc->tcg_ops.debug_excp_handler) {
- cc->tcg_ops.debug_excp_handler(cpu);
+ if (cc->tcg_ops->debug_excp_handler) {
+ cc->tcg_ops->debug_excp_handler(cpu);
}
}
@@ -547,7 +548,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.do_interrupt(cpu);
+ cc->tcg_ops->do_interrupt(cpu);
#endif
*ret = cpu->exception_index;
cpu->exception_index = -1;
@@ -556,7 +557,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (replay_exception()) {
CPUClass *cc = CPU_GET_CLASS(cpu);
qemu_mutex_lock_iothread();
- cc->tcg_ops.do_interrupt(cpu);
+ cc->tcg_ops->do_interrupt(cpu);
qemu_mutex_unlock_iothread();
cpu->exception_index = -1;
@@ -655,8 +656,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
- if (cc->tcg_ops.cpu_exec_interrupt &&
- cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) {
+ if (cc->tcg_ops->cpu_exec_interrupt &&
+ cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
@@ -834,7 +835,7 @@ void tcg_exec_realizefn(CPUState *cpu, Error **errp)
CPUClass *cc = CPU_GET_CLASS(cpu);
if (!tcg_target_initialized) {
- cc->tcg_ops.initialize();
+ cc->tcg_ops->initialize();
tcg_target_initialized = true;
}
tlb_init(cpu);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b7717803b8..8a7b779270 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
@@ -1305,11 +1306,37 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
* This is not a probe, so only valid return is success; failure
* should result in exception + longjmp to the cpu loop.
*/
- ok = cc->tcg_ops.tlb_fill(cpu, addr, size,
- access_type, mmu_idx, false, retaddr);
+ ok = cc->tcg_ops->tlb_fill(cpu, addr, size,
+ access_type, mmu_idx, false, retaddr);
assert(ok);
}
+static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+}
+
+static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response,
+ uintptr_t retaddr)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!cpu->ignore_memory_transaction_failures &&
+ cc->tcg_ops->do_transaction_failed) {
+ cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size,
+ access_type, mmu_idx, attrs,
+ response, retaddr);
+ }
+}
+
static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
int mmu_idx, target_ulong addr, uintptr_t retaddr,
MMUAccessType access_type, MemOp op)
@@ -1577,8 +1604,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
CPUState *cs = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cs);
- if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
- mmu_idx, nonfault, retaddr)) {
+ if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
+ mmu_idx, nonfault, retaddr)) {
/* Non-faulting page table read failed. */
*phost = NULL;
return TLB_INVALID_MASK;
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 9e6e188d19..0b6f56ca40 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
@@ -187,8 +188,8 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.tlb_fill(cpu, address, 0, access_type,
- MMU_USER_IDX, false, pc);
+ cc->tcg_ops->tlb_fill(cpu, address, 0, access_type,
+ MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
@@ -218,8 +219,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
} else {
CPUState *cpu = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type,
- MMU_USER_IDX, false, ra);
+ cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type,
+ MMU_USER_IDX, false, ra);
g_assert_not_reached();
}
}
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 46c71a0ac8..83c8086062 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -53,6 +53,9 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/help_option.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
enum jazz_model_e {
JAZZ_MAGNUM,
@@ -209,8 +212,8 @@ static void mips_jazz_init(MachineState *machine,
*/
cc = CPU_GET_CLASS(cpu);
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
- cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
+ real_do_transaction_failed = cc->tcg_ops->do_transaction_failed;
+ cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
/* allocate RAM */
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index e85059f9c6..7b1eeafdb0 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -24,6 +24,11 @@
#include "qemu/cutils.h"
#include "qemu/cacheflush.h"
#include "cpu.h"
+
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
+
#include "exec/exec-all.h"
#include "exec/target_page.h"
#include "hw/qdev-core.h"
@@ -894,9 +899,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
return;
}
- if (cc->tcg_ops.adjust_watchpoint_address) {
+ if (cc->tcg_ops->adjust_watchpoint_address) {
/* this is currently used only by ARM BE32 */
- addr = cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len);
+ addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
}
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (watchpoint_address_matches(wp, addr, len)
@@ -917,8 +922,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;
if (!cpu->watchpoint_hit) {
- if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoint &&
- !cc->tcg_ops.debug_check_watchpoint(cpu, wp)) {
+ if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint &&
+ !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 0710298e5a..27192b62e2 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,20 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps alpha_tcg_ops = {
+ .initialize = alpha_translate_init,
+ .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
+ .tlb_fill = alpha_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = alpha_cpu_do_interrupt,
+ .do_transaction_failed = alpha_cpu_do_transaction_failed,
+ .do_unaligned_access = alpha_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void alpha_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -217,22 +231,17 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
- cc->tcg_ops.do_interrupt = alpha_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
- cc->tcg_ops.initialize = alpha_translate_init;
+ cc->tcg_ops = &alpha_tcg_ops;
cc->gdb_num_core_regs = 67;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c9a66d3103..8790a92797 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -26,6 +26,9 @@
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "cpu.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
#include "internals.h"
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
@@ -55,8 +58,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
}
#ifdef CONFIG_TCG
-static void arm_cpu_synchronize_from_tb(CPUState *cs,
- const TranslationBlock *tb)
+void arm_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -590,7 +593,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
return true;
}
@@ -2242,6 +2245,28 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifdef CONFIG_TCG
+/*
+ * NB: cannot be const, as some elements are changed for specific
+ * arm cpu classes.
+ */
+static struct TCGCPUOps arm_tcg_ops = {
+ .initialize = arm_translate_init,
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = arm_cpu_exec_interrupt,
+ .tlb_fill = arm_cpu_tlb_fill,
+ .debug_excp_handler = arm_debug_excp_handler,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = arm_cpu_do_interrupt,
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -2274,19 +2299,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
+
#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = arm_translate_init;
- cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
- cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
- cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
- cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
-#if !defined(CONFIG_USER_ONLY)
- cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
- cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
- cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
- cc->tcg_ops.debug_check_watchpoint = arm_debug_check_watchpoint;
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+ cc->tcg_ops = &arm_tcg_ops;
#endif /* CONFIG_TCG */
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a9a1cdb871..10c5118176 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -21,6 +21,9 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
#include "qemu/module.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
@@ -805,10 +808,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
-#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
-#endif /* CONFIG_TCG */
-
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index d9c160f1ac..c29b434c60 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -10,6 +10,9 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
#include "internals.h"
/* CPU models. These are not needed for the AArch64 linux-user build. */
@@ -34,7 +37,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
cs->exception_index = EXCP_IRQ;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
ret = true;
}
return ret;
@@ -660,6 +663,24 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
+#ifdef CONFIG_TCG
+static struct TCGCPUOps arm_v7m_tcg_ops = {
+ .initialize = arm_translate_init,
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
+ .tlb_fill = arm_cpu_tlb_fill,
+ .debug_excp_handler = arm_debug_excp_handler,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -667,10 +688,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
acc->info = data;
#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
-#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_interrupt = arm_v7m_cpu_do_interrupt;
-#endif
+ cc->tcg_ops = &arm_v7m_tcg_ops;
#endif /* CONFIG_TCG */
cc->gdb_core_xml_file = "arm-m-profile.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 476e645b37..fa0f8e0e80 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,19 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps avr_tcg_ops = {
+ .initialize = avr_cpu_tcg_init,
+ .synchronize_from_tb = avr_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = avr_cpu_exec_interrupt,
+ .tlb_fill = avr_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = avr_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void avr_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -198,21 +211,17 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = avr_cpu_class_by_name;
cc->has_work = avr_cpu_has_work;
- cc->tcg_ops.do_interrupt = avr_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->tcg_ops.tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
- cc->tcg_ops.initialize = avr_cpu_tcg_init;
- cc->tcg_ops.synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "avr-cpu.xml";
+ cc->tcg_ops = &avr_tcg_ops;
}
/*
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 69d3b6181f..65880b9928 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/address-spaces.h"
#include "exec/helper-proto.h"
@@ -34,7 +35,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_RESET) {
if (cpu_interrupts_enabled(env)) {
cs->exception_index = EXCP_RESET;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
@@ -45,7 +46,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
int index = ctz32(env->intsrc);
cs->exception_index = EXCP_INT(index);
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
env->intsrc &= env->intsrc - 1; /* clear the interrupt */
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index b65743e8ca..ed983380fc 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,15 +193,36 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps crisv10_tcg_ops = {
+ .initialize = cris_initialize_crisv10_tcg,
+ .cpu_exec_interrupt = cris_cpu_exec_interrupt,
+ .tlb_fill = cris_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = crisv10_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static struct TCGCPUOps crisv32_tcg_ops = {
+ .initialize = cris_initialize_tcg,
+ .cpu_exec_interrupt = cris_cpu_exec_interrupt,
+ .tlb_fill = cris_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = cris_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 8;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
@@ -210,9 +231,8 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
@@ -221,9 +241,8 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 10;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
@@ -232,9 +251,8 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 11;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
@@ -243,16 +261,17 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 17;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 32;
+ cc->tcg_ops = &crisv32_tcg_ops;
}
static void cris_cpu_class_init(ObjectClass *oc, void *data)
@@ -268,13 +287,10 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
- cc->tcg_ops.do_interrupt = cris_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
@@ -284,7 +300,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
- cc->tcg_ops.initialize = cris_initialize_tcg;
}
#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/cris/helper.c b/target/cris/helper.c
index 1f4d6f7d45..7e3bb58fe1 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "mmu.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
@@ -299,7 +300,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
cs->exception_index = EXCP_IRQ;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
ret = true;
}
if (interrupt_request & CPU_INTERRUPT_NMI) {
@@ -311,7 +312,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
cs->exception_index = EXCP_NMI;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
ret = true;
}
}
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index fd7f849a1c..d8fad52d1f 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,20 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps hppa_tcg_ops = {
+ .initialize = hppa_translate_init,
+ .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
+ .tlb_fill = hppa_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = hppa_cpu_do_interrupt,
+ .do_unaligned_access = hppa_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void hppa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -142,23 +156,17 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
- cc->tcg_ops.do_interrupt = hppa_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access;
dc->vmsd = &vmstate_hppa_cpu;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
- cc->tcg_ops.initialize = hppa_translate_init;
-
cc->gdb_num_core_regs = 128;
+ cc->tcg_ops = &hppa_tcg_ops;
}
static const TypeInfo hppa_cpu_type_info = {
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 4a53cd89e2..1e125d2175 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -57,16 +57,22 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.eip = tb->pc - tb->cs_base;
}
-void tcg_cpu_common_class_init(CPUClass *cc)
-{
- cc->tcg_ops.do_interrupt = x86_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
- cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
- cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
- cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
- cc->tcg_ops.initialize = tcg_x86_init;
- cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps x86_tcg_ops = {
+ .initialize = tcg_x86_init,
+ .synchronize_from_tb = x86_cpu_synchronize_from_tb,
+ .cpu_exec_enter = x86_cpu_exec_enter,
+ .cpu_exec_exit = x86_cpu_exec_exit,
+ .cpu_exec_interrupt = x86_cpu_exec_interrupt,
+ .do_interrupt = x86_cpu_do_interrupt,
+ .tlb_fill = x86_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.debug_excp_handler = breakpoint_handler;
-#endif
+ .debug_excp_handler = breakpoint_handler,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+void tcg_cpu_common_class_init(CPUClass *cc)
+{
+ cc->tcg_ops = &x86_tcg_ops;
}
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index fb3761b749..c23d72874c 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,19 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps lm32_tcg_ops = {
+ .initialize = lm32_translate_init,
+ .cpu_exec_interrupt = lm32_cpu_exec_interrupt,
+ .tlb_fill = lm32_cpu_tlb_fill,
+ .debug_excp_handler = lm32_debug_excp_handler,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = lm32_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void lm32_cpu_class_init(ObjectClass *oc, void *data)
{
LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
@@ -222,22 +235,18 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
- cc->tcg_ops.do_interrupt = lm32_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = lm32_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
- cc->tcg_ops.debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
- cc->tcg_ops.initialize = lm32_translate_init;
+ cc->tcg_ops = &lm32_tcg_ops;
}
#define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index e68b933c84..c6fde8132b 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -453,6 +453,19 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps m68k_tcg_ops = {
+ .initialize = m68k_tcg_init,
+ .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
+ .tlb_fill = m68k_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = m68k_cpu_do_interrupt,
+ .do_transaction_failed = m68k_cpu_transaction_failed,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void m68k_cpu_class_init(ObjectClass *c, void *data)
{
M68kCPUClass *mcc = M68K_CPU_CLASS(c);
@@ -465,22 +478,18 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
- cc->tcg_ops.do_interrupt = m68k_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
- cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
- cc->tcg_ops.initialize = m68k_tcg_init;
cc->gdb_num_core_regs = 18;
+ cc->tcg_ops = &m68k_tcg_ops;
}
static void m68k_cpu_class_init_cf_core(ObjectClass *c, void *data)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 6678310f51..433ba20203 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,21 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps mb_tcg_ops = {
+ .initialize = mb_tcg_init,
+ .synchronize_from_tb = mb_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = mb_cpu_exec_interrupt,
+ .tlb_fill = mb_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = mb_cpu_do_interrupt,
+ .do_transaction_failed = mb_cpu_transaction_failed,
+ .do_unaligned_access = mb_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -364,17 +379,13 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
- cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
+
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
+
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
- cc->tcg_ops.do_unaligned_access = mb_cpu_do_unaligned_access;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
@@ -382,7 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 32 + 27;
cc->disas_set_info = mb_disas_set_info;
- cc->tcg_ops.initialize = mb_tcg_init;
+ cc->tcg_ops = &mb_tcg_ops;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 1e93e295cc..ad163ead62 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -663,6 +663,26 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+/*
+ * NB: cannot be const, as some elements are changed for specific
+ * mips hardware (see hw/mips/jazz.c).
+ */
+static struct TCGCPUOps mips_tcg_ops = {
+ .initialize = mips_tcg_init,
+ .synchronize_from_tb = mips_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = mips_cpu_exec_interrupt,
+ .tlb_fill = mips_cpu_tlb_fill,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = mips_cpu_do_interrupt,
+ .do_transaction_failed = mips_cpu_do_transaction_failed,
+ .do_unaligned_access = mips_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void mips_cpu_class_init(ObjectClass *c, void *data)
{
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
@@ -685,21 +705,11 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->vmsd = &vmstate_mips_cpu;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
-#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = mips_tcg_init;
- cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
- cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
- cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
-#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
-
-#endif /* CONFIG_USER_ONLY */
-#endif /* CONFIG_TCG */
-
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &mips_tcg_ops;
+#endif /* CONFIG_TCG */
}
static const TypeInfo mips_cpu_type_info = {
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 36bef4d357..83bec34d36 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,17 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps moxie_tcg_ops = {
+ .initialize = moxie_translate_init,
+ .tlb_fill = moxie_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = moxie_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void moxie_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -107,16 +118,14 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = moxie_cpu_class_by_name;
cc->has_work = moxie_cpu_has_work;
- cc->tcg_ops.do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
- cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
- cc->tcg_ops.initialize = moxie_translate_init;
+ cc->tcg_ops = &moxie_tcg_ops;
}
static void moxielite_initfn(Object *obj)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index c43aa3d4c4..e9c9fc3a38 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,18 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps nios2_tcg_ops = {
+ .initialize = nios2_tcg_init,
+ .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
+ .tlb_fill = nios2_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = nios2_cpu_do_interrupt,
+ .do_unaligned_access = nios2_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
static void nios2_cpu_class_init(ObjectClass *oc, void *data)
{
@@ -221,20 +233,16 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
- cc->tcg_ops.do_interrupt = nios2_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
- cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
cc->gdb_num_core_regs = 49;
- cc->tcg_ops.initialize = nios2_tcg_init;
+ cc->tcg_ops = &nios2_tcg_ops;
}
static const TypeInfo nios2_cpu_type_info = {
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 1a31f7564f..2c64842f46 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,18 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps openrisc_tcg_ops = {
+ .initialize = openrisc_translate_init,
+ .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
+ .tlb_fill = openrisc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = openrisc_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
{
OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
@@ -186,20 +198,17 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
- cc->tcg_ops.do_interrupt = openrisc_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = openrisc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
- cc->tcg_ops.initialize = openrisc_translate_init;
cc->disas_set_info = openrisc_disas_set_info;
+ cc->tcg_ops = &openrisc_tcg_ops;
}
/* Sort alphabetically by type name, except for "any". */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5e85fd58b6..16f1a34238 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -580,6 +580,21 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps riscv_tcg_ops = {
+ .initialize = riscv_translate_init,
+ .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+ .tlb_fill = riscv_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = riscv_cpu_do_interrupt,
+ .do_transaction_failed = riscv_cpu_do_transaction_failed,
+ .do_unaligned_access = riscv_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -593,11 +608,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
- cc->tcg_ops.do_interrupt = riscv_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 33;
@@ -609,16 +621,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
- cc->tcg_ops.initialize = riscv_translate_init;
- cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill;
+ cc->tcg_ops = &riscv_tcg_ops;
device_class_set_props(dc, riscv_cpu_properties);
}
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index e79f009cbd..7ac6618b26 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,19 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps rx_tcg_ops = {
+ .initialize = rx_translate_init,
+ .synchronize_from_tb = rx_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = rx_cpu_exec_interrupt,
+ .tlb_fill = rx_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = rx_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void rx_cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -186,20 +199,17 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
- cc->tcg_ops.do_interrupt = rx_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
+
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
- cc->tcg_ops.initialize = rx_translate_init;
- cc->tcg_ops.tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "rx-core.xml";
+ cc->tcg_ops = &rx_tcg_ops;
}
static const TypeInfo rx_cpu_info = {
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index a723ede8d1..d35eb39a1b 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,22 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps s390_tcg_ops = {
+ .initialize = s390x_translate_init,
+ .tlb_fill = s390_cpu_tlb_fill,
+
+#if !defined(CONFIG_USER_ONLY)
+ .cpu_exec_interrupt = s390_cpu_exec_interrupt,
+ .do_interrupt = s390_cpu_do_interrupt,
+ .debug_excp_handler = s390x_cpu_debug_excp_handler,
+ .do_unaligned_access = s390x_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void s390_cpu_class_init(ObjectClass *oc, void *data)
{
S390CPUClass *scc = S390_CPU_CLASS(oc);
@@ -495,9 +511,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
scc->reset = s390_cpu_reset;
cc->class_by_name = s390_cpu_class_by_name,
cc->has_work = s390_cpu_has_work;
-#ifdef CONFIG_TCG
- cc->tcg_ops.do_interrupt = s390_cpu_do_interrupt;
-#endif
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
cc->gdb_read_register = s390_cpu_gdb_read_register;
@@ -507,23 +520,17 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
-#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
- cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
- cc->tcg_ops.do_unaligned_access = s390x_cpu_do_unaligned_access;
-#endif
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
-#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = s390x_translate_init;
- cc->tcg_ops.tlb_fill = s390_cpu_tlb_fill;
-#endif
-
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
cc->gdb_core_xml_file = "s390x-core64.xml";
cc->gdb_arch_name = s390_gdb_arch_name;
s390_cpu_model_class_register_props(oc);
+
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &s390_tcg_ops;
+#endif /* CONFIG_TCG */
}
static const TypeInfo s390_cpu_type_info = {
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 292152b562..a78d283bc8 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -206,6 +206,20 @@ static const VMStateDescription vmstate_sh_cpu = {
.unmigratable = 1,
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps superh_tcg_ops = {
+ .initialize = sh4_translate_init,
+ .synchronize_from_tb = superh_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = superh_cpu_exec_interrupt,
+ .tlb_fill = superh_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = superh_cpu_do_interrupt,
+ .do_unaligned_access = superh_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void superh_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -219,24 +233,19 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
- cc->tcg_ops.do_interrupt = superh_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
- cc->tcg_ops.initialize = sh4_translate_init;
cc->gdb_num_core_regs = 59;
dc->vmsd = &vmstate_sh_cpu;
+ cc->tcg_ops = &superh_tcg_ops;
}
#define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 1b785f60df..aece2c7dc8 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,23 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps sparc_tcg_ops = {
+ .initialize = sparc_tcg_init,
+ .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
+ .tlb_fill = sparc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = sparc_cpu_do_interrupt,
+ .do_transaction_failed = sparc_cpu_do_transaction_failed,
+ .do_unaligned_access = sparc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void sparc_cpu_class_init(ObjectClass *oc, void *data)
{
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
@@ -863,31 +880,25 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
- cc->tcg_ops.do_interrupt = sparc_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
#endif
cc->set_pc = sparc_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
- cc->tcg_ops.initialize = sparc_tcg_init;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_num_core_regs = 86;
#else
cc->gdb_num_core_regs = 72;
#endif
+ cc->tcg_ops = &sparc_tcg_ops;
}
static const TypeInfo sparc_cpu_type_info = {
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 7d4ead4ef1..d969c2f133 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -134,6 +134,18 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps tilegx_tcg_ops = {
+ .initialize = tilegx_tcg_init,
+ .cpu_exec_interrupt = tilegx_cpu_exec_interrupt,
+ .tlb_fill = tilegx_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = tilegx_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -147,13 +159,10 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
- cc->tcg_ops.do_interrupt = tilegx_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
- cc->tcg_ops.tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
- cc->tcg_ops.initialize = tilegx_tcg_init;
+ cc->tcg_ops = &tilegx_tcg_ops;
}
static const TypeInfo tilegx_cpu_type_info = {
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 9b21b640e2..0b1e139bcb 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,14 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps tricore_tcg_ops = {
+ .initialize = tricore_tcg_init,
+ .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
+ .tlb_fill = tricore_cpu_tlb_fill,
+};
+
static void tricore_cpu_class_init(ObjectClass *c, void *data)
{
TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
@@ -162,10 +170,8 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
- cc->tcg_ops.initialize = tricore_tcg_init;
- cc->tcg_ops.tlb_fill = tricore_cpu_tlb_fill;
+ cc->tcg_ops = &tricore_tcg_ops;
}
#define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index e27ffc571a..0258884f84 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,18 @@ static const VMStateDescription vmstate_uc32_cpu = {
.unmigratable = 1,
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps uc32_tcg_ops = {
+ .initialize = uc32_translate_init,
+ .cpu_exec_interrupt = uc32_cpu_exec_interrupt,
+ .tlb_fill = uc32_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = uc32_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void uc32_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -131,14 +143,11 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
- cc->tcg_ops.do_interrupt = uc32_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->tcg_ops.tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
+ cc->tcg_ops = &uc32_tcg_ops;
}
#define DEFINE_UNICORE32_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 4b6381569f..e2b2c7a71c 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,21 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.unmigratable = 1,
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps xtensa_tcg_ops = {
+ .initialize = xtensa_translate_init,
+ .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
+ .tlb_fill = xtensa_cpu_tlb_fill,
+ .debug_excp_handler = xtensa_breakpoint_handler,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = xtensa_cpu_do_interrupt,
+ .do_transaction_failed = xtensa_cpu_do_transaction_failed,
+ .do_unaligned_access = xtensa_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -194,23 +209,17 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
- cc->tcg_ops.do_interrupt = xtensa_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
- cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
- cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
- cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
+ cc->tcg_ops = &xtensa_tcg_ops;
}
static const TypeInfo xtensa_cpu_type_info = {
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 27ab243c6e..9867d0a6e4 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10827,6 +10827,23 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps ppc_tcg_ops = {
+ .initialize = ppc_translate_init,
+ .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+ .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = ppc_cpu_do_interrupt,
+ .cpu_exec_enter = ppc_cpu_exec_enter,
+ .cpu_exec_exit = ppc_cpu_exec_exit,
+ .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void ppc_cpu_class_init(ObjectClass *oc, void *data)
{
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
@@ -10878,21 +10895,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
-#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = ppc_translate_init;
- cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
- cc->tcg_ops.do_interrupt = ppc_cpu_do_interrupt;
- cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
-#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
- cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
- cc->tcg_ops.do_unaligned_access = ppc_cpu_do_unaligned_access;
-#endif /* !CONFIG_USER_ONLY */
-#endif /* CONFIG_TCG */
-
cc->disas_set_info = ppc_disas_set_info;
dc->fw_name = "PowerPC,UNKNOWN";
+
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &ppc_tcg_ops;
+#endif /* CONFIG_TCG */
}
static const TypeInfo ppc_cpu_type_info = {
diff --git a/MAINTAINERS b/MAINTAINERS
index 34359a99b8..862df04e95 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -129,6 +129,7 @@ F: include/exec/helper*.h
F: include/exec/tb-hash.h
F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
+F: include/hw/core/tcg-cpu-ops.h
FPU emulation
M: Aurelien Jarno <aurelien@aurel32.net>
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-01-28 9:28 ` [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Claudio Fontana
@ 2021-01-29 0:31 ` Richard Henderson
2021-01-29 9:00 ` Claudio Fontana
2021-02-02 10:01 ` Claudio Fontana
0 siblings, 2 replies; 44+ messages in thread
From: Richard Henderson @ 2021-01-29 0:31 UTC (permalink / raw)
To: Claudio Fontana, Alex Bennée, Paolo Bonzini,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Alistair Francis, Roman Bolshakov,
qemu-devel
On 1/27/21 11:28 PM, Claudio Fontana wrote:
> + /*
> + * NB: this should be covered by CONFIG_TCG, but it is unsafe to do it here,
> + * as this header is included by both ss_specific and ss_common code,
> + * leading to potential differences in the data structure between modules.
> + * We could always keep it last, but it seems safer to just leave this
> + * pointer NULL for non-TCG.
> + */
> + struct TCGCPUOps *tcg_ops;
Sorry, I'm going to unqueue the patch set.
I first thought this was fixing up something done already, fixing an existing bug.
But it's something done in patch 1, and therefore the patch set needs to be
re-worked to use this pointer to begin, for the exact reasons detailed above.
Otherwise it would appear this breaks bisection.
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-01-29 0:31 ` Richard Henderson
@ 2021-01-29 9:00 ` Claudio Fontana
2021-01-29 19:19 ` Richard Henderson
2021-02-02 10:01 ` Claudio Fontana
1 sibling, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-29 9:00 UTC (permalink / raw)
To: Richard Henderson, Alex Bennée, Paolo Bonzini,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Alistair Francis, Roman Bolshakov,
qemu-devel
On 1/29/21 1:31 AM, Richard Henderson wrote:
> On 1/27/21 11:28 PM, Claudio Fontana wrote:
>> + /*
>> + * NB: this should be covered by CONFIG_TCG, but it is unsafe to do it here,
>> + * as this header is included by both ss_specific and ss_common code,
>> + * leading to potential differences in the data structure between modules.
>> + * We could always keep it last, but it seems safer to just leave this
>> + * pointer NULL for non-TCG.
>> + */
>> + struct TCGCPUOps *tcg_ops;
>
> Sorry, I'm going to unqueue the patch set.
>
> I first thought this was fixing up something done already, fixing an existing bug.
>
> But it's something done in patch 1, and therefore the patch set needs to be
> re-worked to use this pointer to begin, for the exact reasons detailed above.
> Otherwise it would appear this breaks bisection.
>
>
> r~
>
Hi Richard,
I made sure that the previous patches actually work in practice,
ie the issue mentioned there does not actually happen in practice,
due to the purposeful placement of the field in the structure that might be seen by one module
and not the other at the end of the structure, so no problem happens, and bisection
is actually safe.
The warning and the change is due to the fact that changing things in the way this patch
suggests makes it safer from _future changes_,
in which someone might add a new field at the end of the structure, after the conditional fields,
which would actually break things.
Do you think I should redo the series anyway? I would have started this way in the first place,
but I tried not to redo Eduardo's work.
Let me know what you think,
Thanks,
Claudio
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-01-29 9:00 ` Claudio Fontana
@ 2021-01-29 19:19 ` Richard Henderson
2021-01-29 19:36 ` Eduardo Habkost
0 siblings, 1 reply; 44+ messages in thread
From: Richard Henderson @ 2021-01-29 19:19 UTC (permalink / raw)
To: Claudio Fontana, Alex Bennée, Paolo Bonzini,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Alistair Francis, Roman Bolshakov,
qemu-devel
On 1/28/21 11:00 PM, Claudio Fontana wrote:
> Do you think I should redo the series anyway? I would have started this way
> in the first place, but I tried not to redo Eduardo's work.
I think that would be a good idea, yes.
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-01-29 19:19 ` Richard Henderson
@ 2021-01-29 19:36 ` Eduardo Habkost
2021-01-30 9:40 ` Claudio Fontana
0 siblings, 1 reply; 44+ messages in thread
From: Eduardo Habkost @ 2021-01-29 19:36 UTC (permalink / raw)
To: Richard Henderson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth,
Philippe Mathieu-Daudé,
qemu-devel, Roman Bolshakov, Alistair Francis, Claudio Fontana,
Paolo Bonzini, Alex Bennée
On Fri, Jan 29, 2021 at 09:19:00AM -1000, Richard Henderson wrote:
> On 1/28/21 11:00 PM, Claudio Fontana wrote:
> > Do you think I should redo the series anyway? I would have started this way
> > in the first place, but I tried not to redo Eduardo's work.
> I think that would be a good idea, yes.
Maybe just removing the #ifdefs from patch 01 (which were not
present in the patch I wrote) could be a way to avoid redoing the
whole series.
--
Eduardo
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-01-29 19:36 ` Eduardo Habkost
@ 2021-01-30 9:40 ` Claudio Fontana
0 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-30 9:40 UTC (permalink / raw)
To: Eduardo Habkost, Richard Henderson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth,
Philippe Mathieu-Daudé,
qemu-devel, Roman Bolshakov, Alistair Francis, Paolo Bonzini,
Alex Bennée
On 1/29/21 8:36 PM, Eduardo Habkost wrote:
> On Fri, Jan 29, 2021 at 09:19:00AM -1000, Richard Henderson wrote:
>> On 1/28/21 11:00 PM, Claudio Fontana wrote:
>>> Do you think I should redo the series anyway? I would have started this way
>>> in the first place, but I tried not to redo Eduardo's work.
>> I think that would be a good idea, yes.
>
> Maybe just removing the #ifdefs from patch 01 (which were not
> present in the patch I wrote) could be a way to avoid redoing the
> whole series.
>
That's a good point, I'll give it a try,
thanks!
Claudio
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-01-29 0:31 ` Richard Henderson
2021-01-29 9:00 ` Claudio Fontana
@ 2021-02-02 10:01 ` Claudio Fontana
2021-02-02 10:27 ` Claudio Fontana
1 sibling, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-02-02 10:01 UTC (permalink / raw)
To: Richard Henderson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Philippe Mathieu-Daudé,
qemu-devel, Roman Bolshakov, Alistair Francis, Paolo Bonzini,
Alex Bennée
On 1/29/21 1:31 AM, Richard Henderson wrote:
> On 1/27/21 11:28 PM, Claudio Fontana wrote:
>> + /*
>> + * NB: this should be covered by CONFIG_TCG, but it is unsafe to do it here,
>> + * as this header is included by both ss_specific and ss_common code,
>> + * leading to potential differences in the data structure between modules.
>> + * We could always keep it last, but it seems safer to just leave this
>> + * pointer NULL for non-TCG.
>> + */
>> + struct TCGCPUOps *tcg_ops;
>
> Sorry, I'm going to unqueue the patch set.
>
> I first thought this was fixing up something done already, fixing an existing bug.
>
> But it's something done in patch 1, and therefore the patch set needs to be
> re-worked to use this pointer to begin, for the exact reasons detailed above.
> Otherwise it would appear this breaks bisection.
>
>
> r~
>
Hello Richard,
I reworked this as suggested by Eduardo:, by not making the fields conditional at all in the first part of the series.
This should remove any doubt about potential issues. In no case is bisection compromised.
Are you ok with this?
Thanks,
Claudio
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-02-02 10:01 ` Claudio Fontana
@ 2021-02-02 10:27 ` Claudio Fontana
0 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-02-02 10:27 UTC (permalink / raw)
To: Richard Henderson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Alex Bennée, qemu-devel, Roman Bolshakov, Alistair Francis,
Paolo Bonzini, Philippe Mathieu-Daudé
On 2/2/21 11:01 AM, Claudio Fontana wrote:
> On 1/29/21 1:31 AM, Richard Henderson wrote:
>> On 1/27/21 11:28 PM, Claudio Fontana wrote:
>>> + /*
>>> + * NB: this should be covered by CONFIG_TCG, but it is unsafe to do it here,
>>> + * as this header is included by both ss_specific and ss_common code,
>>> + * leading to potential differences in the data structure between modules.
>>> + * We could always keep it last, but it seems safer to just leave this
>>> + * pointer NULL for non-TCG.
>>> + */
>>> + struct TCGCPUOps *tcg_ops;
>>
>> Sorry, I'm going to unqueue the patch set.
>>
>> I first thought this was fixing up something done already, fixing an existing bug.
>>
>> But it's something done in patch 1, and therefore the patch set needs to be
>> re-worked to use this pointer to begin, for the exact reasons detailed above.
>> Otherwise it would appear this breaks bisection.
>>
>>
>> r~
>>
>
> Hello Richard,
>
> I reworked this as suggested by Eduardo:, by not making the fields conditional at all in the first part of the series.
>
> This should remove any doubt about potential issues. In no case is bisection compromised.
>
> Are you ok with this?
>
> Thanks,
>
> Claudio
>
Respinned with this change as v15:
https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg00045.html
Thanks,
Claudio
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v14 16/22] accel: extend AccelState and AccelClass to user-mode
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (14 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 17/22] accel: replace struct CpusAccel with AccelOpsClass Claudio Fontana
` (6 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
[claudio: rebased on Richard's splitwx work]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/boards.h | 2 +-
include/{sysemu => qemu}/accel.h | 14 +++++----
include/sysemu/hvf.h | 2 +-
include/sysemu/kvm.h | 2 +-
include/sysemu/kvm_int.h | 2 +-
target/i386/hvf/hvf-i386.h | 2 +-
accel/accel-common.c | 50 ++++++++++++++++++++++++++++++
accel/{accel.c => accel-softmmu.c} | 27 ++--------------
accel/accel-user.c | 24 ++++++++++++++
accel/qtest/qtest.c | 2 +-
accel/tcg/tcg-all.c | 15 +++++++--
accel/xen/xen-all.c | 2 +-
bsd-user/main.c | 6 +++-
linux-user/main.c | 6 +++-
softmmu/memory.c | 2 +-
softmmu/qtest.c | 2 +-
softmmu/vl.c | 2 +-
target/i386/hax/hax-all.c | 2 +-
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86_task.c | 2 +-
target/i386/whpx/whpx-all.c | 2 +-
MAINTAINERS | 2 +-
accel/meson.build | 4 ++-
accel/tcg/meson.build | 2 +-
24 files changed, 125 insertions(+), 53 deletions(-)
rename include/{sysemu => qemu}/accel.h (95%)
create mode 100644 accel/accel-common.c
rename accel/{accel.c => accel-softmmu.c} (75%)
create mode 100644 accel/accel-user.c
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 17b1f3f0b9..85af4faf76 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -6,7 +6,7 @@
#include "exec/memory.h"
#include "sysemu/hostmem.h"
#include "sysemu/blockdev.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qapi/qapi-types-machine.h"
#include "qemu/module.h"
#include "qom/object.h"
diff --git a/include/sysemu/accel.h b/include/qemu/accel.h
similarity index 95%
rename from include/sysemu/accel.h
rename to include/qemu/accel.h
index e08b8ab8fa..fac4a18703 100644
--- a/include/sysemu/accel.h
+++ b/include/qemu/accel.h
@@ -20,8 +20,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#ifndef HW_ACCEL_H
-#define HW_ACCEL_H
+#ifndef QEMU_ACCEL_H
+#define QEMU_ACCEL_H
#include "qom/object.h"
#include "exec/hwaddr.h"
@@ -37,8 +37,8 @@ typedef struct AccelClass {
/*< public >*/
const char *name;
-#ifndef CONFIG_USER_ONLY
int (*init_machine)(MachineState *ms);
+#ifndef CONFIG_USER_ONLY
void (*setup_post)(MachineState *ms, AccelState *accel);
bool (*has_memory)(MachineState *ms, AddressSpace *as,
hwaddr start_addr, hwaddr size);
@@ -67,11 +67,13 @@ typedef struct AccelClass {
OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL)
AccelClass *accel_find(const char *opt_name);
+AccelState *current_accel(void);
+
+#ifndef CONFIG_USER_ONLY
int accel_init_machine(AccelState *accel, MachineState *ms);
/* Called just before os_setup_post (ie just before drop OS privs) */
void accel_setup_post(MachineState *ms);
+#endif /* !CONFIG_USER_ONLY */
-AccelState *current_accel(void);
-
-#endif
+#endif /* QEMU_ACCEL_H */
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index f893768df9..c98636bc81 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -13,7 +13,7 @@
#ifndef HVF_H
#define HVF_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef CONFIG_HVF
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index bb5d5cf497..739682f3c3 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -17,7 +17,7 @@
#include "qemu/queue.h"
#include "hw/core/cpu.h"
#include "exec/memattrs.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef NEED_CPU_H
diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
index 65740806da..ccb8869f01 100644
--- a/include/sysemu/kvm_int.h
+++ b/include/sysemu/kvm_int.h
@@ -10,7 +10,7 @@
#define QEMU_KVM_INT_H
#include "exec/memory.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/kvm.h"
typedef struct KVMSlot
diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h
index e0edffd077..50b914fd67 100644
--- a/target/i386/hvf/hvf-i386.h
+++ b/target/i386/hvf/hvf-i386.h
@@ -16,7 +16,7 @@
#ifndef HVF_I386_H
#define HVF_I386_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/hvf.h"
#include "cpu.h"
#include "x86.h"
diff --git a/accel/accel-common.c b/accel/accel-common.c
new file mode 100644
index 0000000000..ddec8cb5ae
--- /dev/null
+++ b/accel/accel-common.c
@@ -0,0 +1,50 @@
+/*
+ * QEMU accel class, components common to system emulation and user mode
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2014 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/accel.h"
+
+static const TypeInfo accel_type = {
+ .name = TYPE_ACCEL,
+ .parent = TYPE_OBJECT,
+ .class_size = sizeof(AccelClass),
+ .instance_size = sizeof(AccelState),
+};
+
+/* Lookup AccelClass from opt_name. Returns NULL if not found */
+AccelClass *accel_find(const char *opt_name)
+{
+ char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
+ AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
+ g_free(class_name);
+ return ac;
+}
+
+static void register_accel_types(void)
+{
+ type_register_static(&accel_type);
+}
+
+type_init(register_accel_types);
diff --git a/accel/accel.c b/accel/accel-softmmu.c
similarity index 75%
rename from accel/accel.c
rename to accel/accel-softmmu.c
index cb555e3b06..f89da8f9d1 100644
--- a/accel/accel.c
+++ b/accel/accel-softmmu.c
@@ -1,5 +1,5 @@
/*
- * QEMU System Emulator, accelerator interfaces
+ * QEMU accel class, system emulation components
*
* Copyright (c) 2003-2008 Fabrice Bellard
* Copyright (c) 2014 Red Hat Inc.
@@ -24,28 +24,12 @@
*/
#include "qemu/osdep.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/boards.h"
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
#include "qom/object.h"
-static const TypeInfo accel_type = {
- .name = TYPE_ACCEL,
- .parent = TYPE_OBJECT,
- .class_size = sizeof(AccelClass),
- .instance_size = sizeof(AccelState),
-};
-
-/* Lookup AccelClass from opt_name. Returns NULL if not found */
-AccelClass *accel_find(const char *opt_name)
-{
- char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
- AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
- g_free(class_name);
- return ac;
-}
-
int accel_init_machine(AccelState *accel, MachineState *ms)
{
AccelClass *acc = ACCEL_GET_CLASS(accel);
@@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms)
acc->setup_post(ms, accel);
}
}
-
-static void register_accel_types(void)
-{
- type_register_static(&accel_type);
-}
-
-type_init(register_accel_types);
diff --git a/accel/accel-user.c b/accel/accel-user.c
new file mode 100644
index 0000000000..26bdda6236
--- /dev/null
+++ b/accel/accel-user.c
@@ -0,0 +1,24 @@
+/*
+ * QEMU accel class, user-mode components
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/accel.h"
+
+AccelState *current_accel(void)
+{
+ static AccelState *accel;
+
+ if (!accel) {
+ AccelClass *ac = accel_find("tcg");
+
+ g_assert(ac != NULL);
+ accel = ACCEL(object_new_with_class(OBJECT_CLASS(ac)));
+ }
+ return accel;
+}
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index b282cea5cf..b4e731cb2b 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
@@ -17,7 +17,7 @@
#include "qemu/module.h"
#include "qemu/option.h"
#include "qemu/config-file.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/qtest.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 2eea8c32ee..642a7b94a7 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -30,9 +30,12 @@
#include "tcg/tcg.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
-#include "hw/boards.h"
+#include "qemu/accel.h"
#include "qapi/qapi-builtin-visit.h"
+
+#ifndef CONFIG_USER_ONLY
#include "tcg-cpus.h"
+#endif /* CONFIG_USER_ONLY */
struct TCGState {
AccelState parent_obj;
@@ -97,7 +100,7 @@ static void tcg_accel_instance_init(Object *obj)
s->mttcg_enabled = default_mttcg_enabled();
/* If debugging enabled, default "auto on", otherwise off. */
-#ifdef CONFIG_DEBUG_TCG
+#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY)
s->splitwx_enabled = -1;
#else
s->splitwx_enabled = 0;
@@ -114,8 +117,12 @@ static int tcg_init(MachineState *ms)
mttcg_enabled = s->mttcg_enabled;
/*
- * Initialize TCG regions
+ * Initialize TCG regions only for softmmu.
+ *
+ * This needs to be done later for user mode, because the prologue
+ * generation needs to be delayed so that GUEST_BASE is already set.
*/
+#ifndef CONFIG_USER_ONLY
tcg_region_init();
if (mttcg_enabled) {
@@ -125,6 +132,8 @@ static int tcg_init(MachineState *ms)
} else {
cpus_register_accel(&tcg_cpus_rr);
}
+#endif /* !CONFIG_USER_ONLY */
+
return 0;
}
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
index 878a4089d9..594aaf6b49 100644
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -15,7 +15,7 @@
#include "hw/xen/xen-legacy-backend.h"
#include "hw/xen/xen_pt.h"
#include "chardev/char.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/cpus.h"
#include "sysemu/xen.h"
#include "sysemu/runstate.h"
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 65163e1396..6501164e05 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/units.h"
+#include "qemu/accel.h"
#include "sysemu/tcg.h"
#include "qemu-version.h"
#include <machine/trap.h>
@@ -909,8 +910,11 @@ int main(int argc, char **argv)
}
/* init tcg before creating CPUs and to get qemu_host_page_size */
- tcg_exec_init(0, false);
+ {
+ AccelClass *ac = ACCEL_GET_CLASS(current_accel());
+ ac->init_machine(NULL);
+ }
cpu_type = parse_cpu_option(cpu_model);
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
diff --git a/linux-user/main.c b/linux-user/main.c
index bb4e55e8fc..7ed23d9a29 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/units.h"
+#include "qemu/accel.h"
#include "sysemu/tcg.h"
#include "qemu-version.h"
#include <sys/syscall.h>
@@ -701,8 +702,11 @@ int main(int argc, char **argv, char **envp)
cpu_type = parse_cpu_option(cpu_model);
/* init tcg before creating CPUs and to get qemu_host_page_size */
- tcg_exec_init(0, false);
+ {
+ AccelClass *ac = ACCEL_GET_CLASS(current_accel());
+ ac->init_machine(NULL);
+ }
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
cpu_reset(cpu);
diff --git a/softmmu/memory.c b/softmmu/memory.c
index 333e1ed7b0..3381cfe308 100644
--- a/softmmu/memory.c
+++ b/softmmu/memory.c
@@ -32,7 +32,7 @@
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "sysemu/tcg.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/boards.h"
#include "migration/vmstate.h"
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 7965dc9a16..130c366615 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -20,7 +20,7 @@
#include "exec/ioport.h"
#include "exec/memory.h"
#include "hw/irq.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/cpu-timers.h"
#include "qemu/config-file.h"
#include "qemu/option.h"
diff --git a/softmmu/vl.c b/softmmu/vl.c
index a8876b8965..4f48d03d0d 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -44,7 +44,7 @@
#include "qemu/error-report.h"
#include "qemu/sockets.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/usb.h"
#include "hw/isa/isa.h"
#include "hw/scsi/scsi.h"
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index fecfe8cd6e..d7f4bb44a7 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -28,7 +28,7 @@
#include "exec/address-spaces.h"
#include "qemu-common.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "hw/boards.h"
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index ed9356565c..ffc9efa40f 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -69,7 +69,7 @@
#include "exec/address-spaces.h"
#include "hw/i386/apic_internal.h"
#include "qemu/main-loop.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "target/i386/cpu.h"
#include "hvf-cpus.h"
diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
index 6f04478b3a..d66dfd7669 100644
--- a/target/i386/hvf/x86_task.c
+++ b/target/i386/hvf/x86_task.c
@@ -28,7 +28,7 @@
#include "hw/i386/apic_internal.h"
#include "qemu/main-loop.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "target/i386/cpu.h"
// TODO: taskswitch handling
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 985ceba8f8..aa5c876138 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -13,7 +13,7 @@
#include "exec/address-spaces.h"
#include "exec/ioport.h"
#include "qemu-common.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/whpx.h"
#include "sysemu/cpus.h"
#include "sysemu/runstate.h"
diff --git a/MAINTAINERS b/MAINTAINERS
index 862df04e95..dbeb19fc59 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -438,7 +438,7 @@ Overall
M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
-F: include/sysemu/accel.h
+F: include/qemu/accel.h
F: accel/accel.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/accel/meson.build b/accel/meson.build
index b26cca227a..b44ba30c86 100644
--- a/accel/meson.build
+++ b/accel/meson.build
@@ -1,4 +1,6 @@
-softmmu_ss.add(files('accel.c'))
+specific_ss.add(files('accel-common.c'))
+softmmu_ss.add(files('accel-softmmu.c'))
+user_ss.add(files('accel-user.c'))
subdir('qtest')
subdir('kvm')
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index f39aab0a0c..424d9bb1fc 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,5 +1,6 @@
tcg_ss = ss.source_set()
tcg_ss.add(files(
+ 'tcg-all.c',
'cpu-exec-common.c',
'cpu-exec.c',
'tcg-runtime-gvec.c',
@@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
- 'tcg-all.c',
'cputlb.c',
'tcg-cpus.c',
'tcg-cpus-mttcg.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 17/22] accel: replace struct CpusAccel with AccelOpsClass
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (15 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 16/22] accel: extend AccelState and AccelClass to user-mode Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
` (5 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
also centralize the registration of the cpus.c module
accelerator operations in accel/accel-softmmu.c
Consequently, rename all tcg-cpus.c, kvm-cpus.c etc to
tcg-accel-ops.c, kvm-accel-ops.c etc, also matching the
object type names.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
accel/accel-softmmu.h | 15 ++++++
accel/kvm/kvm-cpus.h | 2 -
...g-cpus-icount.h => tcg-accel-ops-icount.h} | 2 +
accel/tcg/tcg-accel-ops-mttcg.h | 19 ++++++++
.../tcg/{tcg-cpus-rr.h => tcg-accel-ops-rr.h} | 0
accel/tcg/{tcg-cpus.h => tcg-accel-ops.h} | 6 +--
include/qemu/accel.h | 2 +
include/sysemu/accel-ops.h | 45 ++++++++++++++++++
include/sysemu/cpus.h | 26 ++--------
.../i386/hax/{hax-cpus.h => hax-accel-ops.h} | 2 -
target/i386/hax/hax-windows.h | 2 +-
.../i386/hvf/{hvf-cpus.h => hvf-accel-ops.h} | 2 -
.../whpx/{whpx-cpus.h => whpx-accel-ops.h} | 2 -
accel/accel-common.c | 11 +++++
accel/accel-softmmu.c | 43 +++++++++++++++--
accel/kvm/{kvm-cpus.c => kvm-accel-ops.c} | 26 +++++++---
accel/kvm/kvm-all.c | 2 -
accel/qtest/qtest.c | 23 ++++++---
...g-cpus-icount.c => tcg-accel-ops-icount.c} | 21 +++------
...tcg-cpus-mttcg.c => tcg-accel-ops-mttcg.c} | 14 ++----
.../tcg/{tcg-cpus-rr.c => tcg-accel-ops-rr.c} | 13 ++---
accel/tcg/{tcg-cpus.c => tcg-accel-ops.c} | 47 ++++++++++++++++++-
accel/tcg/tcg-all.c | 12 -----
accel/xen/xen-all.c | 22 ++++++---
bsd-user/main.c | 3 +-
linux-user/main.c | 1 +
softmmu/cpus.c | 12 ++---
softmmu/vl.c | 7 ++-
.../i386/hax/{hax-cpus.c => hax-accel-ops.c} | 31 ++++++++----
target/i386/hax/hax-all.c | 5 +-
target/i386/hax/hax-mem.c | 2 +-
target/i386/hax/hax-posix.c | 2 +-
target/i386/hax/hax-windows.c | 2 +-
.../i386/hvf/{hvf-cpus.c => hvf-accel-ops.c} | 29 +++++++++---
target/i386/hvf/hvf.c | 3 +-
target/i386/hvf/x86hvf.c | 2 +-
.../whpx/{whpx-cpus.c => whpx-accel-ops.c} | 31 ++++++++----
target/i386/whpx/whpx-all.c | 7 +--
MAINTAINERS | 3 +-
accel/kvm/meson.build | 2 +-
accel/tcg/meson.build | 8 ++--
target/i386/hax/meson.build | 2 +-
target/i386/hvf/meson.build | 2 +-
target/i386/whpx/meson.build | 2 +-
44 files changed, 353 insertions(+), 162 deletions(-)
create mode 100644 accel/accel-softmmu.h
rename accel/tcg/{tcg-cpus-icount.h => tcg-accel-ops-icount.h} (88%)
create mode 100644 accel/tcg/tcg-accel-ops-mttcg.h
rename accel/tcg/{tcg-cpus-rr.h => tcg-accel-ops-rr.h} (100%)
rename accel/tcg/{tcg-cpus.h => tcg-accel-ops.h} (72%)
create mode 100644 include/sysemu/accel-ops.h
rename target/i386/hax/{hax-cpus.h => hax-accel-ops.h} (95%)
rename target/i386/hvf/{hvf-cpus.h => hvf-accel-ops.h} (94%)
rename target/i386/whpx/{whpx-cpus.h => whpx-accel-ops.h} (96%)
rename accel/kvm/{kvm-cpus.c => kvm-accel-ops.c} (72%)
rename accel/tcg/{tcg-cpus-icount.c => tcg-accel-ops-icount.c} (89%)
rename accel/tcg/{tcg-cpus-mttcg.c => tcg-accel-ops-mttcg.c} (92%)
rename accel/tcg/{tcg-cpus-rr.c => tcg-accel-ops-rr.c} (97%)
rename accel/tcg/{tcg-cpus.c => tcg-accel-ops.c} (63%)
rename target/i386/hax/{hax-cpus.c => hax-accel-ops.c} (69%)
rename target/i386/hvf/{hvf-cpus.c => hvf-accel-ops.c} (84%)
rename target/i386/whpx/{whpx-cpus.c => whpx-accel-ops.c} (71%)
diff --git a/accel/accel-softmmu.h b/accel/accel-softmmu.h
new file mode 100644
index 0000000000..2877b5c234
--- /dev/null
+++ b/accel/accel-softmmu.h
@@ -0,0 +1,15 @@
+/*
+ * QEMU System Emulation accel internal functions
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_SOFTMMU_H
+#define ACCEL_SOFTMMU_H
+
+void accel_init_ops_interfaces(AccelClass *ac);
+
+#endif /* ACCEL_SOFTMMU_H */
diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h
index 3df732b816..bf0bd1bee4 100644
--- a/accel/kvm/kvm-cpus.h
+++ b/accel/kvm/kvm-cpus.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel kvm_cpus;
-
int kvm_init_vcpu(CPUState *cpu, Error **errp);
int kvm_cpu_exec(CPUState *cpu);
void kvm_destroy_vcpu(CPUState *cpu);
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-accel-ops-icount.h
similarity index 88%
rename from accel/tcg/tcg-cpus-icount.h
rename to accel/tcg/tcg-accel-ops-icount.h
index b695939dfa..d884aa2aaa 100644
--- a/accel/tcg/tcg-cpus-icount.h
+++ b/accel/tcg/tcg-accel-ops-icount.h
@@ -14,4 +14,6 @@ void icount_handle_deadline(void);
void icount_prepare_for_run(CPUState *cpu);
void icount_process_data(CPUState *cpu);
+void icount_handle_interrupt(CPUState *cpu, int mask);
+
#endif /* TCG_CPUS_ICOUNT_H */
diff --git a/accel/tcg/tcg-accel-ops-mttcg.h b/accel/tcg/tcg-accel-ops-mttcg.h
new file mode 100644
index 0000000000..0af91dd3b3
--- /dev/null
+++ b/accel/tcg/tcg-accel-ops-mttcg.h
@@ -0,0 +1,19 @@
+/*
+ * QEMU TCG Multi Threaded vCPUs implementation
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPUS_MTTCG_H
+#define TCG_CPUS_MTTCG_H
+
+/* kick MTTCG vCPU thread */
+void mttcg_kick_vcpu_thread(CPUState *cpu);
+
+/* start an mttcg vCPU thread */
+void mttcg_start_vcpu_thread(CPUState *cpu);
+
+#endif /* TCG_CPUS_MTTCG_H */
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-accel-ops-rr.h
similarity index 100%
rename from accel/tcg/tcg-cpus-rr.h
rename to accel/tcg/tcg-accel-ops-rr.h
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-accel-ops.h
similarity index 72%
rename from accel/tcg/tcg-cpus.h
rename to accel/tcg/tcg-accel-ops.h
index d6893a32f8..48130006de 100644
--- a/accel/tcg/tcg-cpus.h
+++ b/accel/tcg/tcg-accel-ops.h
@@ -14,12 +14,8 @@
#include "sysemu/cpus.h"
-extern const CpusAccel tcg_cpus_mttcg;
-extern const CpusAccel tcg_cpus_icount;
-extern const CpusAccel tcg_cpus_rr;
-
void tcg_cpus_destroy(CPUState *cpu);
int tcg_cpus_exec(CPUState *cpu);
-void tcg_cpus_handle_interrupt(CPUState *cpu, int mask);
+void tcg_handle_interrupt(CPUState *cpu, int mask);
#endif /* TCG_CPUS_H */
diff --git a/include/qemu/accel.h b/include/qemu/accel.h
index fac4a18703..b9d6d69eb8 100644
--- a/include/qemu/accel.h
+++ b/include/qemu/accel.h
@@ -69,6 +69,8 @@ typedef struct AccelClass {
AccelClass *accel_find(const char *opt_name);
AccelState *current_accel(void);
+void accel_init_interfaces(AccelClass *ac);
+
#ifndef CONFIG_USER_ONLY
int accel_init_machine(AccelState *accel, MachineState *ms);
diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h
new file mode 100644
index 0000000000..6102d2f80d
--- /dev/null
+++ b/include/sysemu/accel-ops.h
@@ -0,0 +1,45 @@
+/*
+ * Accelerator OPS, used for cpus.c module
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_OPS_H
+#define ACCEL_OPS_H
+
+#include "qom/object.h"
+
+#define ACCEL_OPS_SUFFIX "-ops"
+#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX
+#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS)
+
+typedef struct AccelOpsClass AccelOpsClass;
+DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS)
+
+/* cpus.c operations interface */
+struct AccelOpsClass {
+ /*< private >*/
+ ObjectClass parent_class;
+ /*< public >*/
+
+ /* initialization function called when accel is chosen */
+ void (*ops_init)(AccelOpsClass *ops);
+
+ void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */
+ void (*kick_vcpu_thread)(CPUState *cpu);
+
+ void (*synchronize_post_reset)(CPUState *cpu);
+ void (*synchronize_post_init)(CPUState *cpu);
+ void (*synchronize_state)(CPUState *cpu);
+ void (*synchronize_pre_loadvm)(CPUState *cpu);
+
+ void (*handle_interrupt)(CPUState *cpu, int mask);
+
+ int64_t (*get_virtual_clock)(void);
+ int64_t (*get_elapsed_ticks)(void);
+};
+
+#endif /* ACCEL_OPS_H */
diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h
index e8156728c6..2cd74392e0 100644
--- a/include/sysemu/cpus.h
+++ b/include/sysemu/cpus.h
@@ -2,30 +2,14 @@
#define QEMU_CPUS_H
#include "qemu/timer.h"
+#include "sysemu/accel-ops.h"
-/* cpus.c */
+/* register accel-specific operations */
+void cpus_register_accel(const AccelOpsClass *i);
-/* CPU execution threads */
+/* accel/dummy-cpus.c */
-typedef struct CpusAccel {
- void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY */
- void (*kick_vcpu_thread)(CPUState *cpu);
-
- void (*synchronize_post_reset)(CPUState *cpu);
- void (*synchronize_post_init)(CPUState *cpu);
- void (*synchronize_state)(CPUState *cpu);
- void (*synchronize_pre_loadvm)(CPUState *cpu);
-
- void (*handle_interrupt)(CPUState *cpu, int mask);
-
- int64_t (*get_virtual_clock)(void);
- int64_t (*get_elapsed_ticks)(void);
-} CpusAccel;
-
-/* register accel-specific cpus interface implementation */
-void cpus_register_accel(const CpusAccel *i);
-
-/* Create a dummy vcpu for CpusAccel->create_vcpu_thread */
+/* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */
void dummy_start_vcpu_thread(CPUState *);
/* interface available for cpus accelerator threads */
diff --git a/target/i386/hax/hax-cpus.h b/target/i386/hax/hax-accel-ops.h
similarity index 95%
rename from target/i386/hax/hax-cpus.h
rename to target/i386/hax/hax-accel-ops.h
index ee8ab7a631..c7698519cd 100644
--- a/target/i386/hax/hax-cpus.h
+++ b/target/i386/hax/hax-accel-ops.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel hax_cpus;
-
#include "hax-interface.h"
#include "hax-i386.h"
diff --git a/target/i386/hax/hax-windows.h b/target/i386/hax/hax-windows.h
index a5ce12d663..b1f5d4f32f 100644
--- a/target/i386/hax/hax-windows.h
+++ b/target/i386/hax/hax-windows.h
@@ -23,7 +23,7 @@
#include <winioctl.h>
#include <windef.h>
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
#define HAX_INVALID_FD INVALID_HANDLE_VALUE
diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-accel-ops.h
similarity index 94%
rename from target/i386/hvf/hvf-cpus.h
rename to target/i386/hvf/hvf-accel-ops.h
index ced31b82c0..8f992da168 100644
--- a/target/i386/hvf/hvf-cpus.h
+++ b/target/i386/hvf/hvf-accel-ops.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel hvf_cpus;
-
int hvf_init_vcpu(CPUState *);
int hvf_vcpu_exec(CPUState *);
void hvf_cpu_synchronize_state(CPUState *);
diff --git a/target/i386/whpx/whpx-cpus.h b/target/i386/whpx/whpx-accel-ops.h
similarity index 96%
rename from target/i386/whpx/whpx-cpus.h
rename to target/i386/whpx/whpx-accel-ops.h
index bdb367d1d0..2dee6d61ea 100644
--- a/target/i386/whpx/whpx-cpus.h
+++ b/target/i386/whpx/whpx-accel-ops.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel whpx_cpus;
-
int whpx_init_vcpu(CPUState *cpu);
int whpx_vcpu_exec(CPUState *cpu);
void whpx_destroy_vcpu(CPUState *cpu);
diff --git a/accel/accel-common.c b/accel/accel-common.c
index ddec8cb5ae..6b59873419 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -26,6 +26,10 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
+#ifndef CONFIG_USER_ONLY
+#include "accel-softmmu.h"
+#endif /* !CONFIG_USER_ONLY */
+
static const TypeInfo accel_type = {
.name = TYPE_ACCEL,
.parent = TYPE_OBJECT,
@@ -42,6 +46,13 @@ AccelClass *accel_find(const char *opt_name)
return ac;
}
+void accel_init_interfaces(AccelClass *ac)
+{
+#ifndef CONFIG_USER_ONLY
+ accel_init_ops_interfaces(ac);
+#endif /* !CONFIG_USER_ONLY */
+}
+
static void register_accel_types(void)
{
type_register_static(&accel_type);
diff --git a/accel/accel-softmmu.c b/accel/accel-softmmu.c
index f89da8f9d1..2d15d3f2f4 100644
--- a/accel/accel-softmmu.c
+++ b/accel/accel-softmmu.c
@@ -26,9 +26,9 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
#include "hw/boards.h"
-#include "sysemu/arch_init.h"
-#include "sysemu/sysemu.h"
-#include "qom/object.h"
+#include "sysemu/cpus.h"
+
+#include "accel-softmmu.h"
int accel_init_machine(AccelState *accel, MachineState *ms)
{
@@ -60,3 +60,40 @@ void accel_setup_post(MachineState *ms)
acc->setup_post(ms, accel);
}
}
+
+/* initialize the arch-independent accel operation interfaces */
+void accel_init_ops_interfaces(AccelClass *ac)
+{
+ const char *ac_name;
+ char *ops_name;
+ AccelOpsClass *ops;
+
+ ac_name = object_class_get_name(OBJECT_CLASS(ac));
+ g_assert(ac_name != NULL);
+
+ ops_name = g_strdup_printf("%s" ACCEL_OPS_SUFFIX, ac_name);
+ ops = ACCEL_OPS_CLASS(object_class_by_name(ops_name));
+ g_free(ops_name);
+
+ /*
+ * all accelerators need to define ops, providing at least a mandatory
+ * non-NULL create_vcpu_thread operation.
+ */
+ g_assert(ops != NULL);
+ if (ops->ops_init) {
+ ops->ops_init(ops);
+ }
+ cpus_register_accel(ops);
+}
+
+static const TypeInfo accel_ops_type_info = {
+ .name = TYPE_ACCEL_OPS,
+ .parent = TYPE_OBJECT,
+ .abstract = true,
+ .class_size = sizeof(AccelOpsClass),
+};
+static void accel_softmmu_register_types(void)
+{
+ type_register_static(&accel_ops_type_info);
+}
+type_init(accel_softmmu_register_types);
diff --git a/accel/kvm/kvm-cpus.c b/accel/kvm/kvm-accel-ops.c
similarity index 72%
rename from accel/kvm/kvm-cpus.c
rename to accel/kvm/kvm-accel-ops.c
index d809b1e74c..430d09de03 100644
--- a/accel/kvm/kvm-cpus.c
+++ b/accel/kvm/kvm-accel-ops.c
@@ -74,11 +74,25 @@ static void kvm_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
-const CpusAccel kvm_cpus = {
- .create_vcpu_thread = kvm_start_vcpu_thread,
+static void kvm_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = kvm_cpu_synchronize_post_reset,
- .synchronize_post_init = kvm_cpu_synchronize_post_init,
- .synchronize_state = kvm_cpu_synchronize_state,
- .synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = kvm_start_vcpu_thread;
+ ops->synchronize_post_reset = kvm_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = kvm_cpu_synchronize_post_init;
+ ops->synchronize_state = kvm_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm;
};
+static const TypeInfo kvm_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("kvm"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = kvm_accel_ops_class_init,
+ .abstract = true,
+};
+static void kvm_accel_ops_register_types(void)
+{
+ type_register_static(&kvm_accel_ops_type);
+}
+type_init(kvm_accel_ops_register_types);
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 3feb17d965..5164d838b9 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -2256,8 +2256,6 @@ static int kvm_init(MachineState *ms)
ret = ram_block_discard_disable(true);
assert(!ret);
}
-
- cpus_register_accel(&kvm_cpus);
return 0;
err:
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index b4e731cb2b..edb29f6fa4 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
@@ -25,14 +25,8 @@
#include "qemu/main-loop.h"
#include "hw/core/cpu.h"
-const CpusAccel qtest_cpus = {
- .create_vcpu_thread = dummy_start_vcpu_thread,
- .get_virtual_clock = qtest_get_virtual_clock,
-};
-
static int qtest_init_accel(MachineState *ms)
{
- cpus_register_accel(&qtest_cpus);
return 0;
}
@@ -52,9 +46,26 @@ static const TypeInfo qtest_accel_type = {
.class_init = qtest_accel_class_init,
};
+static void qtest_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->create_vcpu_thread = dummy_start_vcpu_thread;
+ ops->get_virtual_clock = qtest_get_virtual_clock;
+};
+
+static const TypeInfo qtest_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("qtest"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = qtest_accel_ops_class_init,
+ .abstract = true,
+};
+
static void qtest_type_init(void)
{
type_register_static(&qtest_accel_type);
+ type_register_static(&qtest_accel_ops_type);
}
type_init(qtest_type_init);
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-accel-ops-icount.c
similarity index 89%
rename from accel/tcg/tcg-cpus-icount.c
rename to accel/tcg/tcg-accel-ops-icount.c
index 9f45432275..87762b469c 100644
--- a/accel/tcg/tcg-cpus-icount.c
+++ b/accel/tcg/tcg-accel-ops-icount.c
@@ -32,9 +32,9 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
-#include "tcg-cpus-icount.h"
-#include "tcg-cpus-rr.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-icount.h"
+#include "tcg-accel-ops-rr.h"
static int64_t icount_get_limit(void)
{
@@ -93,7 +93,7 @@ void icount_prepare_for_run(CPUState *cpu)
/*
* These should always be cleared by icount_process_data after
* each vCPU execution. However u16.high can be raised
- * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
*/
g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
g_assert(cpu->icount_extra == 0);
@@ -125,23 +125,14 @@ void icount_process_data(CPUState *cpu)
replay_mutex_unlock();
}
-static void icount_handle_interrupt(CPUState *cpu, int mask)
+void icount_handle_interrupt(CPUState *cpu, int mask)
{
int old_mask = cpu->interrupt_request;
- tcg_cpus_handle_interrupt(cpu, mask);
+ tcg_handle_interrupt(cpu, mask);
if (qemu_cpu_is_self(cpu) &&
!cpu->can_do_io
&& (mask & ~old_mask) != 0) {
cpu_abort(cpu, "Raised interrupt while not in I/O function");
}
}
-
-const CpusAccel tcg_cpus_icount = {
- .create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = rr_kick_vcpu_thread,
-
- .handle_interrupt = icount_handle_interrupt,
- .get_virtual_clock = icount_get,
- .get_elapsed_ticks = icount_get,
-};
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
similarity index 92%
rename from accel/tcg/tcg-cpus-mttcg.c
rename to accel/tcg/tcg-accel-ops-mttcg.c
index 9c3767d260..42973fb062 100644
--- a/accel/tcg/tcg-cpus-mttcg.c
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
@@ -32,7 +32,8 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-mttcg.h"
/*
* In the multi-threaded case each vCPU has its own thread. The TLS
@@ -103,12 +104,12 @@ static void *mttcg_cpu_thread_fn(void *arg)
return NULL;
}
-static void mttcg_kick_vcpu_thread(CPUState *cpu)
+void mttcg_kick_vcpu_thread(CPUState *cpu)
{
cpu_exit(cpu);
}
-static void mttcg_start_vcpu_thread(CPUState *cpu)
+void mttcg_start_vcpu_thread(CPUState *cpu)
{
char thread_name[VCPU_THREAD_NAME_SIZE];
@@ -131,10 +132,3 @@ static void mttcg_start_vcpu_thread(CPUState *cpu)
cpu->hThread = qemu_thread_get_handle(cpu->thread);
#endif
}
-
-const CpusAccel tcg_cpus_mttcg = {
- .create_vcpu_thread = mttcg_start_vcpu_thread,
- .kick_vcpu_thread = mttcg_kick_vcpu_thread,
-
- .handle_interrupt = tcg_cpus_handle_interrupt,
-};
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-accel-ops-rr.c
similarity index 97%
rename from accel/tcg/tcg-cpus-rr.c
rename to accel/tcg/tcg-accel-ops-rr.c
index 0181d2e4eb..4a66055e0d 100644
--- a/accel/tcg/tcg-cpus-rr.c
+++ b/accel/tcg/tcg-accel-ops-rr.c
@@ -32,9 +32,9 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
-#include "tcg-cpus-rr.h"
-#include "tcg-cpus-icount.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-rr.h"
+#include "tcg-accel-ops-icount.h"
/* Kick all RR vCPUs */
void rr_kick_vcpu_thread(CPUState *unused)
@@ -296,10 +296,3 @@ void rr_start_vcpu_thread(CPUState *cpu)
cpu->created = true;
}
}
-
-const CpusAccel tcg_cpus_rr = {
- .create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = rr_kick_vcpu_thread,
-
- .handle_interrupt = tcg_cpus_handle_interrupt,
-};
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-accel-ops.c
similarity index 63%
rename from accel/tcg/tcg-cpus.c
rename to accel/tcg/tcg-accel-ops.c
index e335f9f155..3017f66dd7 100644
--- a/accel/tcg/tcg-cpus.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -34,7 +34,10 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-mttcg.h"
+#include "tcg-accel-ops-rr.h"
+#include "tcg-accel-ops-icount.h"
/* common functionality among all TCG variants */
@@ -64,7 +67,7 @@ int tcg_cpus_exec(CPUState *cpu)
}
/* mask must never be zero, except for A20 change call */
-void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
+void tcg_handle_interrupt(CPUState *cpu, int mask)
{
g_assert(qemu_mutex_iothread_locked());
@@ -80,3 +83,43 @@ void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
}
}
+
+static void tcg_accel_ops_init(AccelOpsClass *ops)
+{
+ if (qemu_tcg_mttcg_enabled()) {
+ ops->create_vcpu_thread = mttcg_start_vcpu_thread;
+ ops->kick_vcpu_thread = mttcg_kick_vcpu_thread;
+ ops->handle_interrupt = tcg_handle_interrupt;
+
+ } else if (icount_enabled()) {
+ ops->create_vcpu_thread = rr_start_vcpu_thread;
+ ops->kick_vcpu_thread = rr_kick_vcpu_thread;
+ ops->handle_interrupt = icount_handle_interrupt;
+ ops->get_virtual_clock = icount_get;
+ ops->get_elapsed_ticks = icount_get;
+
+ } else {
+ ops->create_vcpu_thread = rr_start_vcpu_thread;
+ ops->kick_vcpu_thread = rr_kick_vcpu_thread;
+ ops->handle_interrupt = tcg_handle_interrupt;
+ }
+}
+
+static void tcg_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->ops_init = tcg_accel_ops_init;
+};
+static const TypeInfo tcg_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("tcg"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = tcg_accel_ops_class_init,
+ .abstract = true,
+};
+static void tcg_accel_ops_register_types(void)
+{
+ type_register_static(&tcg_accel_ops_type);
+}
+type_init(tcg_accel_ops_register_types);
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 642a7b94a7..e378c2db73 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -33,10 +33,6 @@
#include "qemu/accel.h"
#include "qapi/qapi-builtin-visit.h"
-#ifndef CONFIG_USER_ONLY
-#include "tcg-cpus.h"
-#endif /* CONFIG_USER_ONLY */
-
struct TCGState {
AccelState parent_obj;
@@ -124,14 +120,6 @@ static int tcg_init(MachineState *ms)
*/
#ifndef CONFIG_USER_ONLY
tcg_region_init();
-
- if (mttcg_enabled) {
- cpus_register_accel(&tcg_cpus_mttcg);
- } else if (icount_enabled()) {
- cpus_register_accel(&tcg_cpus_icount);
- } else {
- cpus_register_accel(&tcg_cpus_rr);
- }
#endif /* !CONFIG_USER_ONLY */
return 0;
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
index 594aaf6b49..82fc21f1ce 100644
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -154,10 +154,6 @@ static void xen_setup_post(MachineState *ms, AccelState *accel)
}
}
-const CpusAccel xen_cpus = {
- .create_vcpu_thread = dummy_start_vcpu_thread,
-};
-
static int xen_init(MachineState *ms)
{
MachineClass *mc = MACHINE_GET_CLASS(ms);
@@ -185,9 +181,6 @@ static int xen_init(MachineState *ms)
* opt out of system RAM being allocated by generic code
*/
mc->default_ram_id = NULL;
-
- cpus_register_accel(&xen_cpus);
-
return 0;
}
@@ -222,9 +215,24 @@ static const TypeInfo xen_accel_type = {
.class_init = xen_accel_class_init,
};
+static void xen_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->create_vcpu_thread = dummy_start_vcpu_thread;
+};
+static const TypeInfo xen_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("xen"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = xen_accel_ops_class_init,
+ .abstract = true,
+};
+
static void xen_type_init(void)
{
type_register_static(&xen_accel_type);
+ type_register_static(&xen_accel_ops_type);
}
type_init(xen_type_init);
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 6501164e05..7cc08024e3 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -909,13 +909,14 @@ int main(int argc, char **argv)
#endif
}
+ cpu_type = parse_cpu_option(cpu_model);
/* init tcg before creating CPUs and to get qemu_host_page_size */
{
AccelClass *ac = ACCEL_GET_CLASS(current_accel());
ac->init_machine(NULL);
+ accel_init_interfaces(ac);
}
- cpu_type = parse_cpu_option(cpu_model);
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
diff --git a/linux-user/main.c b/linux-user/main.c
index 7ed23d9a29..2e3c169878 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -706,6 +706,7 @@ int main(int argc, char **argv, char **envp)
AccelClass *ac = ACCEL_GET_CLASS(current_accel());
ac->init_machine(NULL);
+ accel_init_interfaces(ac);
}
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
diff --git a/softmmu/cpus.c b/softmmu/cpus.c
index 1dc20b9dc3..112eba9d54 100644
--- a/softmmu/cpus.c
+++ b/softmmu/cpus.c
@@ -128,7 +128,7 @@ void hw_error(const char *fmt, ...)
/*
* The chosen accelerator is supposed to register this.
*/
-static const CpusAccel *cpus_accel;
+static const AccelOpsClass *cpus_accel;
void cpu_synchronize_all_states(void)
{
@@ -594,11 +594,11 @@ void cpu_remove_sync(CPUState *cpu)
qemu_mutex_lock_iothread();
}
-void cpus_register_accel(const CpusAccel *ca)
+void cpus_register_accel(const AccelOpsClass *ops)
{
- assert(ca != NULL);
- assert(ca->create_vcpu_thread != NULL); /* mandatory */
- cpus_accel = ca;
+ assert(ops != NULL);
+ assert(ops->create_vcpu_thread != NULL); /* mandatory */
+ cpus_accel = ops;
}
void qemu_init_vcpu(CPUState *cpu)
@@ -618,7 +618,7 @@ void qemu_init_vcpu(CPUState *cpu)
cpu_address_space_init(cpu, 0, "cpu-memory", cpu->memory);
}
- /* accelerators all implement the CpusAccel interface */
+ /* accelerators all implement the AccelOpsClass */
g_assert(cpus_accel != NULL && cpus_accel->create_vcpu_thread != NULL);
cpus_accel->create_vcpu_thread(cpu);
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 4f48d03d0d..77d6bd1e5a 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -1726,7 +1726,8 @@ static bool object_create_early(const char *type, QemuOpts *opts)
return false;
}
- /* Allocation of large amounts of memory may delay
+ /*
+ * Allocation of large amounts of memory may delay
* chardev initialization for too long, and trigger timeouts
* on software that waits for a monitor socket to be created
* (e.g. libvirt).
@@ -3497,7 +3498,7 @@ void qemu_init(int argc, char **argv, char **envp)
*
* Machine compat properties: object_set_machine_compat_props().
* Accelerator compat props: object_set_accelerator_compat_props(),
- * called from configure_accelerator().
+ * called from do_configure_accelerator().
*/
machine_class = MACHINE_GET_CLASS(current_machine);
@@ -3519,6 +3520,8 @@ void qemu_init(int argc, char **argv, char **envp)
if (cpu_option) {
current_machine->cpu_type = parse_cpu_option(cpu_option);
}
+ /* NB: for machine none cpu_type could STILL be NULL here! */
+ accel_init_interfaces(ACCEL_GET_CLASS(current_machine->accelerator));
qemu_resolve_machine_memdev();
parse_numa_opts(current_machine);
diff --git a/target/i386/hax/hax-cpus.c b/target/i386/hax/hax-accel-ops.c
similarity index 69%
rename from target/i386/hax/hax-cpus.c
rename to target/i386/hax/hax-accel-ops.c
index f72c85bd49..f66042c61e 100644
--- a/target/i386/hax/hax-cpus.c
+++ b/target/i386/hax/hax-accel-ops.c
@@ -26,7 +26,7 @@
#include "sysemu/cpus.h"
#include "qemu/guest-random.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
static void *hax_cpu_thread_fn(void *arg)
{
@@ -74,12 +74,27 @@ static void hax_start_vcpu_thread(CPUState *cpu)
#endif
}
-const CpusAccel hax_cpus = {
- .create_vcpu_thread = hax_start_vcpu_thread,
- .kick_vcpu_thread = hax_kick_vcpu_thread,
+static void hax_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = hax_cpu_synchronize_post_reset,
- .synchronize_post_init = hax_cpu_synchronize_post_init,
- .synchronize_state = hax_cpu_synchronize_state,
- .synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = hax_start_vcpu_thread;
+ ops->kick_vcpu_thread = hax_kick_vcpu_thread;
+
+ ops->synchronize_post_reset = hax_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = hax_cpu_synchronize_post_init;
+ ops->synchronize_state = hax_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm;
+};
+static const TypeInfo hax_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("hax"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = hax_accel_ops_class_init,
+ .abstract = true,
};
+static void hax_accel_ops_register_types(void)
+{
+ type_register_static(&hax_accel_ops_type);
+}
+type_init(hax_accel_ops_register_types);
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index d7f4bb44a7..bf65ed6fa9 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -33,7 +33,7 @@
#include "sysemu/runstate.h"
#include "hw/boards.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
#define DEBUG_HAX 0
@@ -364,9 +364,6 @@ static int hax_accel_init(MachineState *ms)
!ret ? "working" : "not working",
!ret ? "fast virt" : "emulation");
}
- if (ret == 0) {
- cpus_register_accel(&hax_cpus);
- }
return ret;
}
diff --git a/target/i386/hax/hax-mem.c b/target/i386/hax/hax-mem.c
index 71e637cf16..35495f5e82 100644
--- a/target/i386/hax/hax-mem.c
+++ b/target/i386/hax/hax-mem.c
@@ -13,7 +13,7 @@
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
#include "qemu/queue.h"
#define DEBUG_HAX_MEM 0
diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c
index 735a749d4b..ac1a51096e 100644
--- a/target/i386/hax/hax-posix.c
+++ b/target/i386/hax/hax-posix.c
@@ -15,7 +15,7 @@
#include <sys/ioctl.h>
#include "sysemu/cpus.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
hax_fd hax_mod_open(void)
{
diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c
index 6c82dfb54f..59afa213a6 100644
--- a/target/i386/hax/hax-windows.c
+++ b/target/i386/hax/hax-windows.c
@@ -12,7 +12,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
/*
* return 0 when success, -1 when driver not loaded,
diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-accel-ops.c
similarity index 84%
rename from target/i386/hvf/hvf-cpus.c
rename to target/i386/hvf/hvf-accel-ops.c
index 817b3d7452..cbaad238e0 100644
--- a/target/i386/hvf/hvf-cpus.c
+++ b/target/i386/hvf/hvf-accel-ops.c
@@ -55,7 +55,7 @@
#include "target/i386/cpu.h"
#include "qemu/guest-random.h"
-#include "hvf-cpus.h"
+#include "hvf-accel-ops.h"
/*
* The HVF-specific vCPU thread function. This one should only run when the host
@@ -121,11 +121,26 @@ static void hvf_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
-const CpusAccel hvf_cpus = {
- .create_vcpu_thread = hvf_start_vcpu_thread,
+static void hvf_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = hvf_cpu_synchronize_post_reset,
- .synchronize_post_init = hvf_cpu_synchronize_post_init,
- .synchronize_state = hvf_cpu_synchronize_state,
- .synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = hvf_start_vcpu_thread;
+
+ ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = hvf_cpu_synchronize_post_init;
+ ops->synchronize_state = hvf_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm;
+};
+static const TypeInfo hvf_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("hvf"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = hvf_accel_ops_class_init,
+ .abstract = true,
};
+static void hvf_accel_ops_register_types(void)
+{
+ type_register_static(&hvf_accel_ops_type);
+}
+type_init(hvf_accel_ops_register_types);
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index ffc9efa40f..5b90dcdf88 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -72,7 +72,7 @@
#include "qemu/accel.h"
#include "target/i386/cpu.h"
-#include "hvf-cpus.h"
+#include "hvf-accel-ops.h"
HVFState *hvf_state;
@@ -887,7 +887,6 @@ static int hvf_accel_init(MachineState *ms)
hvf_state = s;
memory_listener_register(&hvf_memory_listener, &address_space_memory);
- cpus_register_accel(&hvf_cpus);
return 0;
}
diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c
index bbec412b6c..0d7533742e 100644
--- a/target/i386/hvf/x86hvf.c
+++ b/target/i386/hvf/x86hvf.c
@@ -32,7 +32,7 @@
#include <Hypervisor/hv.h>
#include <Hypervisor/hv_vmx.h>
-#include "hvf-cpus.h"
+#include "hvf-accel-ops.h"
void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg,
SegmentCache *qseg, bool is_tr)
diff --git a/target/i386/whpx/whpx-cpus.c b/target/i386/whpx/whpx-accel-ops.c
similarity index 71%
rename from target/i386/whpx/whpx-cpus.c
rename to target/i386/whpx/whpx-accel-ops.c
index f7e69881a3..2b35d6cec4 100644
--- a/target/i386/whpx/whpx-cpus.c
+++ b/target/i386/whpx/whpx-accel-ops.c
@@ -16,7 +16,7 @@
#include "sysemu/whpx.h"
#include "whpx-internal.h"
-#include "whpx-cpus.h"
+#include "whpx-accel-ops.h"
static void *whpx_cpu_thread_fn(void *arg)
{
@@ -83,12 +83,27 @@ static void whpx_kick_vcpu_thread(CPUState *cpu)
}
}
-const CpusAccel whpx_cpus = {
- .create_vcpu_thread = whpx_start_vcpu_thread,
- .kick_vcpu_thread = whpx_kick_vcpu_thread,
+static void whpx_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = whpx_cpu_synchronize_post_reset,
- .synchronize_post_init = whpx_cpu_synchronize_post_init,
- .synchronize_state = whpx_cpu_synchronize_state,
- .synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = whpx_start_vcpu_thread;
+ ops->kick_vcpu_thread = whpx_kick_vcpu_thread;
+
+ ops->synchronize_post_reset = whpx_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = whpx_cpu_synchronize_post_init;
+ ops->synchronize_state = whpx_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm;
+};
+static const TypeInfo whpx_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("whpx"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = whpx_accel_ops_class_init,
+ .abstract = true,
};
+static void whpx_accel_ops_register_types(void)
+{
+ type_register_static(&whpx_accel_ops_type);
+}
+type_init(whpx_accel_ops_register_types);
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index aa5c876138..f0a35df3bb 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -28,8 +28,11 @@
#include "migration/blocker.h"
#include <winerror.h>
-#include "whpx-cpus.h"
#include "whpx-internal.h"
+#include "whpx-accel-ops.h"
+
+#include <WinHvPlatform.h>
+#include <WinHvEmulation.h>
#define HYPERV_APIC_BUS_FREQUENCY (200000000ULL)
@@ -1846,8 +1849,6 @@ static int whpx_accel_init(MachineState *ms)
whpx_memory_init();
- cpus_register_accel(&whpx_cpus);
-
printf("Windows Hypervisor Platform accelerator is operational\n");
return 0;
diff --git a/MAINTAINERS b/MAINTAINERS
index dbeb19fc59..4cc8d9e502 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -439,7 +439,8 @@ M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
-F: accel/accel.c
+F: include/sysemu/accel-ops.h
+F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/accel/kvm/meson.build b/accel/kvm/meson.build
index 7e9dafe24c..8d219bea50 100644
--- a/accel/kvm/meson.build
+++ b/accel/kvm/meson.build
@@ -1,7 +1,7 @@
kvm_ss = ss.source_set()
kvm_ss.add(files(
'kvm-all.c',
- 'kvm-cpus.c',
+ 'kvm-accel-ops.c',
))
kvm_ss.add(when: 'CONFIG_SEV', if_false: files('sev-stub.c'))
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 424d9bb1fc..1236ac7b91 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -15,8 +15,8 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
- 'tcg-cpus.c',
- 'tcg-cpus-mttcg.c',
- 'tcg-cpus-icount.c',
- 'tcg-cpus-rr.c'
+ 'tcg-accel-ops.c',
+ 'tcg-accel-ops-mttcg.c',
+ 'tcg-accel-ops-icount.c',
+ 'tcg-accel-ops-rr.c'
))
diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build
index 77ea431b30..d6c520fb6b 100644
--- a/target/i386/hax/meson.build
+++ b/target/i386/hax/meson.build
@@ -1,7 +1,7 @@
i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
'hax-all.c',
'hax-mem.c',
- 'hax-cpus.c',
+ 'hax-accel-ops.c',
))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build
index 409c9a3f14..e9eb5a5da8 100644
--- a/target/i386/hvf/meson.build
+++ b/target/i386/hvf/meson.build
@@ -1,6 +1,6 @@
i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files(
'hvf.c',
- 'hvf-cpus.c',
+ 'hvf-accel-ops.c',
'x86.c',
'x86_cpuid.c',
'x86_decode.c',
diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build
index d8aa683999..95fc31eb81 100644
--- a/target/i386/whpx/meson.build
+++ b/target/i386/whpx/meson.build
@@ -1,5 +1,5 @@
i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
'whpx-all.c',
'whpx-apic.c',
- 'whpx-cpus.c',
+ 'whpx-accel-ops.c',
))
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (16 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 17/22] accel: replace struct CpusAccel with AccelOpsClass Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 13:03 ` Philippe Mathieu-Daudé
2021-01-28 9:28 ` [PATCH v14 19/22] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
` (4 subsequent siblings)
22 siblings, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
add a new optional interface to CPUClass,
which allows accelerators to extend the CPUClass
with additional accelerator-specific initializations.
Add the field before tcg_ops, and mark tcg_ops as
needing to be last in the struct until we rework this
further in a later patch.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/core/accel-cpu.h | 35 +++++++++++++++++++++++++++++
include/hw/core/cpu.h | 1 +
accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
4 files changed, 81 insertions(+)
create mode 100644 include/hw/core/accel-cpu.h
diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
new file mode 100644
index 0000000000..246b3e2fcb
--- /dev/null
+++ b/include/hw/core/accel-cpu.h
@@ -0,0 +1,35 @@
+/*
+ * Accelerator interface, specializes CPUClass
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_CPU_H
+#define ACCEL_CPU_H
+
+/*
+ * these defines cannot be in cpu.h, because we are using
+ * CPU_RESOLVING_TYPE here.
+ * Use this header to define your accelerator-specific
+ * cpu-specific accelerator interfaces.
+ */
+
+#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
+#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
+typedef struct AccelCPUClass AccelCPUClass;
+DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
+
+typedef struct AccelCPUClass {
+ /*< private >*/
+ ObjectClass parent_class;
+ /*< public >*/
+
+ void (*cpu_class_init)(CPUClass *cc);
+ void (*cpu_instance_init)(CPUState *cpu);
+ void (*cpu_realizefn)(CPUState *cpu, Error **errp);
+} AccelCPUClass;
+
+#endif /* ACCEL_CPU_H */
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 500e2c4fce..81153c349f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -190,6 +190,7 @@ struct CPUClass {
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+ struct AccelCPUClass *accel_cpu;
/*
* NB: this should be covered by CONFIG_TCG, but it is unsafe to do it here,
diff --git a/accel/accel-common.c b/accel/accel-common.c
index 6b59873419..9901b0531c 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -26,6 +26,9 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
+#include "cpu.h"
+#include "hw/core/accel-cpu.h"
+
#ifndef CONFIG_USER_ONLY
#include "accel-softmmu.h"
#endif /* !CONFIG_USER_ONLY */
@@ -46,16 +49,57 @@ AccelClass *accel_find(const char *opt_name)
return ac;
}
+static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
+{
+ CPUClass *cc = CPU_CLASS(klass);
+ AccelCPUClass *accel_cpu = opaque;
+
+ cc->accel_cpu = accel_cpu;
+ if (accel_cpu->cpu_class_init) {
+ accel_cpu->cpu_class_init(cc);
+ }
+}
+
+/* initialize the arch-specific accel CpuClass interfaces */
+static void accel_init_cpu_interfaces(AccelClass *ac)
+{
+ const char *ac_name; /* AccelClass name */
+ char *acc_name; /* AccelCPUClass name */
+ ObjectClass *acc; /* AccelCPUClass */
+
+ ac_name = object_class_get_name(OBJECT_CLASS(ac));
+ g_assert(ac_name != NULL);
+
+ acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE);
+ acc = object_class_by_name(acc_name);
+ g_free(acc_name);
+
+ if (acc) {
+ object_class_foreach(accel_init_cpu_int_aux,
+ CPU_RESOLVING_TYPE, false, acc);
+ }
+}
+
void accel_init_interfaces(AccelClass *ac)
{
#ifndef CONFIG_USER_ONLY
accel_init_ops_interfaces(ac);
#endif /* !CONFIG_USER_ONLY */
+
+ accel_init_cpu_interfaces(ac);
}
+static const TypeInfo accel_cpu_type = {
+ .name = TYPE_ACCEL_CPU,
+ .parent = TYPE_OBJECT,
+ .abstract = true,
+ .class_size = sizeof(AccelCPUClass),
+};
+
static void register_accel_types(void)
{
type_register_static(&accel_type);
+ type_register_static(&accel_cpu_type);
}
type_init(register_accel_types);
diff --git a/MAINTAINERS b/MAINTAINERS
index 4cc8d9e502..1a83b60312 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -440,6 +440,7 @@ R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
F: include/sysemu/accel-ops.h
+F: include/hw/core/accel-cpu.h
F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-28 9:28 ` [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
@ 2021-01-28 13:03 ` Philippe Mathieu-Daudé
2021-01-28 13:22 ` Claudio Fontana
0 siblings, 1 reply; 44+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-28 13:03 UTC (permalink / raw)
To: Claudio Fontana, Alex Bennée, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Peter Maydell,
Markus Armbruster
Cc: Laurent Vivier, Thomas Huth, Alistair Francis, Roman Bolshakov,
qemu-devel
On 1/28/21 10:28 AM, Claudio Fontana wrote:
> add a new optional interface to CPUClass,
> which allows accelerators to extend the CPUClass
> with additional accelerator-specific initializations.
>
> Add the field before tcg_ops, and mark tcg_ops as
> needing to be last in the struct until we rework this
> further in a later patch.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> ---
> include/hw/core/accel-cpu.h | 35 +++++++++++++++++++++++++++++
> include/hw/core/cpu.h | 1 +
> accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> 4 files changed, 81 insertions(+)
> create mode 100644 include/hw/core/accel-cpu.h
>
> diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
> new file mode 100644
> index 0000000000..246b3e2fcb
> --- /dev/null
> +++ b/include/hw/core/accel-cpu.h
> @@ -0,0 +1,35 @@
> +/*
> + * Accelerator interface, specializes CPUClass
> + *
> + * Copyright 2020 SUSE LLC
2020-2021 ;)
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef ACCEL_CPU_H
> +#define ACCEL_CPU_H
> +
> +/*
> + * these defines cannot be in cpu.h, because we are using
> + * CPU_RESOLVING_TYPE here.
> + * Use this header to define your accelerator-specific
> + * cpu-specific accelerator interfaces.
> + */
> +
> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
> +typedef struct AccelCPUClass AccelCPUClass;
> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
> +
> +typedef struct AccelCPUClass {
> + /*< private >*/
> + ObjectClass parent_class;
> + /*< public >*/
> +
> + void (*cpu_class_init)(CPUClass *cc);
> + void (*cpu_instance_init)(CPUState *cpu);
> + void (*cpu_realizefn)(CPUState *cpu, Error **errp);
If we want callers to check errp, better have the prototype return
a boolean.
> +} AccelCPUClass;
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-28 13:03 ` Philippe Mathieu-Daudé
@ 2021-01-28 13:22 ` Claudio Fontana
2021-01-28 16:08 ` Alex Bennée
0 siblings, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 13:22 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Peter Maydell, Markus Armbruster
Cc: Laurent Vivier, Thomas Huth, Alistair Francis, Roman Bolshakov,
qemu-devel
On 1/28/21 2:03 PM, Philippe Mathieu-Daudé wrote:
> On 1/28/21 10:28 AM, Claudio Fontana wrote:
>> add a new optional interface to CPUClass,
>> which allows accelerators to extend the CPUClass
>> with additional accelerator-specific initializations.
>>
>> Add the field before tcg_ops, and mark tcg_ops as
>> needing to be last in the struct until we rework this
>> further in a later patch.
>>
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> ---
>> include/hw/core/accel-cpu.h | 35 +++++++++++++++++++++++++++++
>> include/hw/core/cpu.h | 1 +
>> accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++
>> MAINTAINERS | 1 +
>> 4 files changed, 81 insertions(+)
>> create mode 100644 include/hw/core/accel-cpu.h
>>
>> diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
>> new file mode 100644
>> index 0000000000..246b3e2fcb
>> --- /dev/null
>> +++ b/include/hw/core/accel-cpu.h
>> @@ -0,0 +1,35 @@
>> +/*
>> + * Accelerator interface, specializes CPUClass
>> + *
>> + * Copyright 2020 SUSE LLC
>
> 2020-2021 ;)
Thanks Philippe,
will check them all! It's a bright new year!
>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + */
>> +
>> +#ifndef ACCEL_CPU_H
>> +#define ACCEL_CPU_H
>> +
>> +/*
>> + * these defines cannot be in cpu.h, because we are using
>> + * CPU_RESOLVING_TYPE here.
>> + * Use this header to define your accelerator-specific
>> + * cpu-specific accelerator interfaces.
>> + */
>> +
>> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
>> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
>> +typedef struct AccelCPUClass AccelCPUClass;
>> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
>> +
>> +typedef struct AccelCPUClass {
>> + /*< private >*/
>> + ObjectClass parent_class;
>> + /*< public >*/
>> +
>> + void (*cpu_class_init)(CPUClass *cc);
>> + void (*cpu_instance_init)(CPUState *cpu);
>> + void (*cpu_realizefn)(CPUState *cpu, Error **errp);
>
> If we want callers to check errp, better have the prototype return
> a boolean.
Good point, the whole errp thing is worth revisiting in the series,
there are many cases (which are basically reproduced in the refactoring from existing code),
where errp is passed but is really unused.
I am constantly internally debating whether to remove the parameter altogether, or to keep it in there.
What would you suggest?
>
>> +} AccelCPUClass;
>
>
Thanks for looking at this,
Claudio
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-28 13:22 ` Claudio Fontana
@ 2021-01-28 16:08 ` Alex Bennée
2021-01-28 16:29 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 44+ messages in thread
From: Alex Bennée @ 2021-01-28 16:08 UTC (permalink / raw)
To: Claudio Fontana
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Richard Henderson, Markus Armbruster, qemu-devel,
Roman Bolshakov, Alistair Francis, Paolo Bonzini,
Philippe Mathieu-Daudé
Claudio Fontana <cfontana@suse.de> writes:
> On 1/28/21 2:03 PM, Philippe Mathieu-Daudé wrote:
>> On 1/28/21 10:28 AM, Claudio Fontana wrote:
<snip>
>>> +
>>> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
>>> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
>>> +typedef struct AccelCPUClass AccelCPUClass;
>>> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
>>> +
>>> +typedef struct AccelCPUClass {
>>> + /*< private >*/
>>> + ObjectClass parent_class;
>>> + /*< public >*/
>>> +
>>> + void (*cpu_class_init)(CPUClass *cc);
>>> + void (*cpu_instance_init)(CPUState *cpu);
>>> + void (*cpu_realizefn)(CPUState *cpu, Error **errp);
>>
>> If we want callers to check errp, better have the prototype return
>> a boolean.
>
> Good point, the whole errp thing is worth revisiting in the series,
> there are many cases (which are basically reproduced in the refactoring from existing code),
> where errp is passed but is really unused.
>
> I am constantly internally debating whether to remove the parameter altogether, or to keep it in there.
>
> What would you suggest?
I think it really depends on if we can expect the realizefn to usefully
return an error message that can be read and understood by the user. I
guess this comes down to how much user config is going to be checked at
the point we realize the CPU?
The bool returning realizefn with Error is a fairly common pattern.
>
>>
>>> +} AccelCPUClass;
>>
>>
>
> Thanks for looking at this,
>
> Claudio
--
Alex Bennée
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-28 16:08 ` Alex Bennée
@ 2021-01-28 16:29 ` Philippe Mathieu-Daudé
2021-01-29 0:13 ` Richard Henderson
0 siblings, 1 reply; 44+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-28 16:29 UTC (permalink / raw)
To: Alex Bennée, Claudio Fontana
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Richard Henderson, Markus Armbruster, qemu-devel,
Roman Bolshakov, Alistair Francis, Paolo Bonzini
On 1/28/21 5:08 PM, Alex Bennée wrote:
>
> Claudio Fontana <cfontana@suse.de> writes:
>
>> On 1/28/21 2:03 PM, Philippe Mathieu-Daudé wrote:
>>> On 1/28/21 10:28 AM, Claudio Fontana wrote:
> <snip>
>>>> +
>>>> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
>>>> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
>>>> +typedef struct AccelCPUClass AccelCPUClass;
>>>> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
>>>> +
>>>> +typedef struct AccelCPUClass {
>>>> + /*< private >*/
>>>> + ObjectClass parent_class;
>>>> + /*< public >*/
>>>> +
>>>> + void (*cpu_class_init)(CPUClass *cc);
>>>> + void (*cpu_instance_init)(CPUState *cpu);
>>>> + void (*cpu_realizefn)(CPUState *cpu, Error **errp);
>>>
>>> If we want callers to check errp, better have the prototype return
>>> a boolean.
>>
>> Good point, the whole errp thing is worth revisiting in the series,
>> there are many cases (which are basically reproduced in the refactoring from existing code),
>> where errp is passed but is really unused.
>>
>> I am constantly internally debating whether to remove the parameter altogether, or to keep it in there.
>>
>> What would you suggest?
>
> I think it really depends on if we can expect the realizefn to usefully
> return an error message that can be read and understood by the user. I
> guess this comes down to how much user config is going to be checked at
> the point we realize the CPU?
cpu_realize() is were various feature checks are, isn't it?
-cpu mycpu,feat1=on,feat2=off
CPU 'mycpu' can not disable feature 'feat2' because of REASON.
> The bool returning realizefn with Error is a fairly common pattern.
>
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-28 16:29 ` Philippe Mathieu-Daudé
@ 2021-01-29 0:13 ` Richard Henderson
2021-01-30 10:53 ` Claudio Fontana
0 siblings, 1 reply; 44+ messages in thread
From: Richard Henderson @ 2021-01-29 0:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Alex Bennée, Claudio Fontana
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Markus Armbruster, qemu-devel, Roman Bolshakov, Alistair Francis,
Paolo Bonzini
On 1/28/21 6:29 AM, Philippe Mathieu-Daudé wrote:
> On 1/28/21 5:08 PM, Alex Bennée wrote:
>>
>> Claudio Fontana <cfontana@suse.de> writes:
>>
>>> On 1/28/21 2:03 PM, Philippe Mathieu-Daudé wrote:
>>>> On 1/28/21 10:28 AM, Claudio Fontana wrote:
>> <snip>
>>>>> +
>>>>> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
>>>>> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
>>>>> +typedef struct AccelCPUClass AccelCPUClass;
>>>>> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
>>>>> +
>>>>> +typedef struct AccelCPUClass {
>>>>> + /*< private >*/
>>>>> + ObjectClass parent_class;
>>>>> + /*< public >*/
>>>>> +
>>>>> + void (*cpu_class_init)(CPUClass *cc);
>>>>> + void (*cpu_instance_init)(CPUState *cpu);
>>>>> + void (*cpu_realizefn)(CPUState *cpu, Error **errp);
>>>>
>>>> If we want callers to check errp, better have the prototype return
>>>> a boolean.
>>>
>>> Good point, the whole errp thing is worth revisiting in the series,
>>> there are many cases (which are basically reproduced in the refactoring from existing code),
>>> where errp is passed but is really unused.
>>>
>>> I am constantly internally debating whether to remove the parameter altogether, or to keep it in there.
>>>
>>> What would you suggest?
>>
>> I think it really depends on if we can expect the realizefn to usefully
>> return an error message that can be read and understood by the user. I
>> guess this comes down to how much user config is going to be checked at
>> the point we realize the CPU?
>
> cpu_realize() is were various feature checks are, isn't it?
>
> -cpu mycpu,feat1=on,feat2=off
> CPU 'mycpu' can not disable feature 'feat2' because of REASON.
Yes. And while changing the return type of realize is probably a good idea, it
should be a separate patch.
r~
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-29 0:13 ` Richard Henderson
@ 2021-01-30 10:53 ` Claudio Fontana
2021-01-30 19:01 ` Richard Henderson
0 siblings, 1 reply; 44+ messages in thread
From: Claudio Fontana @ 2021-01-30 10:53 UTC (permalink / raw)
To: Richard Henderson, Philippe Mathieu-Daudé, Alex Bennée
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
qemu-devel, Markus Armbruster, Roman Bolshakov, Alistair Francis,
Paolo Bonzini
On 1/29/21 1:13 AM, Richard Henderson wrote:
> On 1/28/21 6:29 AM, Philippe Mathieu-Daudé wrote:
>> On 1/28/21 5:08 PM, Alex Bennée wrote:
>>>
>>> Claudio Fontana <cfontana@suse.de> writes:
>>>
>>>> On 1/28/21 2:03 PM, Philippe Mathieu-Daudé wrote:
>>>>> On 1/28/21 10:28 AM, Claudio Fontana wrote:
>>> <snip>
>>>>>> +
>>>>>> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
>>>>>> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
>>>>>> +typedef struct AccelCPUClass AccelCPUClass;
>>>>>> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
>>>>>> +
>>>>>> +typedef struct AccelCPUClass {
>>>>>> + /*< private >*/
>>>>>> + ObjectClass parent_class;
>>>>>> + /*< public >*/
>>>>>> +
>>>>>> + void (*cpu_class_init)(CPUClass *cc);
>>>>>> + void (*cpu_instance_init)(CPUState *cpu);
>>>>>> + void (*cpu_realizefn)(CPUState *cpu, Error **errp);
>>>>>
>>>>> If we want callers to check errp, better have the prototype return
>>>>> a boolean.
>>>>
>>>> Good point, the whole errp thing is worth revisiting in the series,
>>>> there are many cases (which are basically reproduced in the refactoring from existing code),
>>>> where errp is passed but is really unused.
>>>>
>>>> I am constantly internally debating whether to remove the parameter altogether, or to keep it in there.
>>>>
>>>> What would you suggest?
>>>
>>> I think it really depends on if we can expect the realizefn to usefully
>>> return an error message that can be read and understood by the user. I
>>> guess this comes down to how much user config is going to be checked at
>>> the point we realize the CPU?
>>
>> cpu_realize() is were various feature checks are, isn't it?
>>
>> -cpu mycpu,feat1=on,feat2=off
>> CPU 'mycpu' can not disable feature 'feat2' because of REASON.
>
> Yes. And while changing the return type of realize is probably a good idea, it
> should be a separate patch.
>
>
> r~
>
To summarize:
1) accel->cpu_realizefn extends the current cpu target-specific realize functions with accelerator-specific code,
which currently does not make use of errp at all (thus, the temptation to remove errp from the interface until it is actually needed by a target).
2) Regarding the target-specific cpu realize functions themselves, registered with the pattern:
device_class_set_parent_realize(dc, x86_cpu_realizefn, &xcc->parent_realize);
device_class_set_parent_realize(dc, arm_cpu_realizefn, &acc->parent_realize);
... etc ...
these currently all return void, and the code that realizes devices (f.e. in hw/core/qdev.c)
calls these callbacks like this:
static void device_set_realized(...)
{
...
if (dc->realize) {
dc->realize(dev, &local_err);
if (local_err != NULL) {
goto fail;
}
}
Ie it does not expect a bool return type for realize().
So making realize return bool means changing all the realize functions for all devices in my view,
which I don't think should be crammed in here..
Wdty?
Thanks,
Claudio
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-30 10:53 ` Claudio Fontana
@ 2021-01-30 19:01 ` Richard Henderson
2021-02-01 9:15 ` Alex Bennée
0 siblings, 1 reply; 44+ messages in thread
From: Richard Henderson @ 2021-01-30 19:01 UTC (permalink / raw)
To: Claudio Fontana, Philippe Mathieu-Daudé, Alex Bennée
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
qemu-devel, Markus Armbruster, Roman Bolshakov, Alistair Francis,
Paolo Bonzini
On 1/30/21 12:53 AM, Claudio Fontana wrote:
> To summarize:
>
> 1) accel->cpu_realizefn extends the current cpu target-specific realize functions with accelerator-specific code,
> which currently does not make use of errp at all (thus, the temptation to remove errp from the interface until it is actually needed by a target).
No, arm does use errp in realizefn already.
It's just that the void return value is hinky.
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-01-30 19:01 ` Richard Henderson
@ 2021-02-01 9:15 ` Alex Bennée
2021-02-01 9:22 ` Claudio Fontana
0 siblings, 1 reply; 44+ messages in thread
From: Alex Bennée @ 2021-02-01 9:15 UTC (permalink / raw)
To: Richard Henderson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Markus Armbruster, qemu-devel, Roman Bolshakov, Alistair Francis,
Claudio Fontana, Paolo Bonzini, Philippe Mathieu-Daudé
Richard Henderson <richard.henderson@linaro.org> writes:
> On 1/30/21 12:53 AM, Claudio Fontana wrote:
>> To summarize:
>>
>> 1) accel->cpu_realizefn extends the current cpu target-specific realize functions with accelerator-specific code,
>> which currently does not make use of errp at all (thus, the temptation to remove errp from the interface until it is actually needed by a target).
>
> No, arm does use errp in realizefn already.
> It's just that the void return value is hinky.
Sounds like fixing the void return would be part of a larger qdev
clean-up rather than this particular series. If I recall there have been
various phases of clean-ups and refactoring of the error code paths in
the past.
>
>
> r~
--
Alex Bennée
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass
2021-02-01 9:15 ` Alex Bennée
@ 2021-02-01 9:22 ` Claudio Fontana
0 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-02-01 9:22 UTC (permalink / raw)
To: Alex Bennée, Richard Henderson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Eduardo Habkost,
Markus Armbruster, qemu-devel, Roman Bolshakov, Alistair Francis,
Paolo Bonzini, Philippe Mathieu-Daudé
On 2/1/21 10:15 AM, Alex Bennée wrote:
>
> Richard Henderson <richard.henderson@linaro.org> writes:
>
>> On 1/30/21 12:53 AM, Claudio Fontana wrote:
>>> To summarize:
>>>
>>> 1) accel->cpu_realizefn extends the current cpu target-specific realize functions with accelerator-specific code,
>>> which currently does not make use of errp at all (thus, the temptation to remove errp from the interface until it is actually needed by a target).
>>
>> No, arm does use errp in realizefn already.
>> It's just that the void return value is hinky.
>
> Sounds like fixing the void return would be part of a larger qdev
> clean-up rather than this particular series. If I recall there have been
> various phases of clean-ups and refactoring of the error code paths in
> the past.
>
>>
>>
>> r~
>
>
I think you are right.
I added a patch in this series to at least not make the problem worse,
by adding a return value to accel_cpu::cpu_realizefn,
and cleaning up the only code path case that signals an error there for now in i386.
(will add as the last patch in the series)
Thanks,
Claudio
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v14 19/22] i386: split cpu accelerators from cpu.c, using AccelCPUClass
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (17 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 20/22] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn Claudio Fontana
` (3 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
i386 is the first user of AccelCPUClass, allowing to split
cpu.c into:
cpu.c cpuid and common x86 cpu functionality
host-cpu.c host x86 cpu functions and "host" cpu type
kvm/kvm-cpu.c KVM x86 AccelCPUClass
hvf/hvf-cpu.c HVF x86 AccelCPUClass
tcg/tcg-cpu.c TCG x86 AccelCPUClass
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/i386/cpu.h | 20 +-
target/i386/host-cpu.h | 19 ++
target/i386/kvm/kvm-cpu.h | 41 ++++
target/i386/tcg/tcg-cpu.h | 15 --
hw/i386/pc_piix.c | 1 +
target/i386/cpu.c | 390 ++++--------------------------------
target/i386/host-cpu.c | 201 +++++++++++++++++++
target/i386/hvf/hvf-cpu.c | 65 ++++++
target/i386/kvm/kvm-cpu.c | 151 ++++++++++++++
target/i386/kvm/kvm.c | 3 +-
target/i386/tcg/tcg-cpu.c | 113 ++++++++++-
MAINTAINERS | 2 +-
target/i386/hvf/meson.build | 1 +
target/i386/kvm/meson.build | 7 +-
target/i386/meson.build | 6 +-
15 files changed, 648 insertions(+), 387 deletions(-)
create mode 100644 target/i386/host-cpu.h
create mode 100644 target/i386/kvm/kvm-cpu.h
delete mode 100644 target/i386/tcg/tcg-cpu.h
create mode 100644 target/i386/host-cpu.c
create mode 100644 target/i386/hvf/hvf-cpu.c
create mode 100644 target/i386/kvm/kvm-cpu.c
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d23a5b340a..5616d2b665 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1909,13 +1909,20 @@ int cpu_x86_signal_handler(int host_signum, void *pinfo,
void *puc);
/* cpu.c */
+void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
+ uint32_t vendor2, uint32_t vendor3);
+typedef struct PropValue {
+ const char *prop, *value;
+} PropValue;
+void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
+
+/* cpu.c other functions (cpuid) */
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx);
void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
-void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
/* helper.c */
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
@@ -2120,17 +2127,6 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
TPRAccess access);
-
-/* Change the value of a KVM-specific default
- *
- * If value is NULL, no default will be set and the original
- * value from the CPU model table will be kept.
- *
- * It is valid to call this function only for properties that
- * are already present in the kvm_default_props table.
- */
-void x86_cpu_change_kvm_default(const char *prop, const char *value);
-
/* Special values for X86CPUVersion: */
/* Resolve to latest CPU version */
diff --git a/target/i386/host-cpu.h b/target/i386/host-cpu.h
new file mode 100644
index 0000000000..d1f2644422
--- /dev/null
+++ b/target/i386/host-cpu.h
@@ -0,0 +1,19 @@
+/*
+ * x86 host CPU type initialization and host CPU functions
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef HOST_CPU_H
+#define HOST_CPU_H
+
+void host_cpu_instance_init(X86CPU *cpu);
+void host_cpu_max_instance_init(X86CPU *cpu);
+void host_cpu_realizefn(CPUState *cs, Error **errp);
+
+void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping);
+
+#endif /* HOST_CPU_H */
diff --git a/target/i386/kvm/kvm-cpu.h b/target/i386/kvm/kvm-cpu.h
new file mode 100644
index 0000000000..e858ca21e5
--- /dev/null
+++ b/target/i386/kvm/kvm-cpu.h
@@ -0,0 +1,41 @@
+/*
+ * i386 KVM CPU type and functions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef KVM_CPU_H
+#define KVM_CPU_H
+
+#ifdef CONFIG_KVM
+/*
+ * Change the value of a KVM-specific default
+ *
+ * If value is NULL, no default will be set and the original
+ * value from the CPU model table will be kept.
+ *
+ * It is valid to call this function only for properties that
+ * are already present in the kvm_default_props table.
+ */
+void x86_cpu_change_kvm_default(const char *prop, const char *value);
+
+#else /* !CONFIG_KVM */
+
+#define x86_cpu_change_kvm_default(a, b)
+
+#endif /* CONFIG_KVM */
+
+#endif /* KVM_CPU_H */
diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h
deleted file mode 100644
index 81f02e562e..0000000000
--- a/target/i386/tcg/tcg-cpu.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * i386 TCG CPU class initialization
- *
- * Copyright 2020 SUSE LLC
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef TCG_CPU_H
-#define TCG_CPU_H
-
-void tcg_cpu_common_class_init(CPUClass *cc);
-
-#endif /* TCG_CPU_H */
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6188c3e97e..3abcb425bb 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -64,6 +64,7 @@
#include "hw/hyperv/vmbus-bridge.h"
#include "hw/mem/nvdimm.h"
#include "hw/i386/acpi-build.h"
+#include "kvm/kvm-cpu.h"
#define MAX_IDE_BUS 2
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 72a79e6019..56a299ef14 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -22,38 +22,25 @@
#include "qemu/cutils.h"
#include "qemu/bitops.h"
#include "qemu/qemu-print.h"
-
#include "cpu.h"
-#include "tcg/tcg-cpu.h"
#include "tcg/helper-tcg.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
#include "sysemu/hvf.h"
-#include "sysemu/cpus.h"
+#include "hw/core/accel-cpu.h"
#include "sysemu/xen.h"
#include "sysemu/whpx.h"
#include "kvm/kvm_i386.h"
#include "sev_i386.h"
-
-#include "qemu/error-report.h"
#include "qemu/module.h"
-#include "qemu/option.h"
-#include "qemu/config-file.h"
-#include "qapi/error.h"
#include "qapi/qapi-visit-machine.h"
#include "qapi/qapi-visit-run-state.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qerror.h"
-#include "qapi/visitor.h"
#include "qom/qom-qobject.h"
-#include "sysemu/arch_init.h"
#include "qapi/qapi-commands-machine-target.h"
-
#include "standard-headers/asm-x86/kvm_para.h"
-
-#include "sysemu/sysemu.h"
-#include "sysemu/tcg.h"
#include "hw/qdev-properties.h"
#include "hw/i386/topology.h"
#ifndef CONFIG_USER_ONLY
@@ -595,8 +582,8 @@ static CPUCacheInfo legacy_l3_cache = {
#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
-static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
- uint32_t vendor2, uint32_t vendor3)
+void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
+ uint32_t vendor2, uint32_t vendor3)
{
int i;
for (i = 0; i < 4; i++) {
@@ -1589,25 +1576,6 @@ void host_cpuid(uint32_t function, uint32_t count,
*edx = vec[3];
}
-void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
-{
- uint32_t eax, ebx, ecx, edx;
-
- host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
-
- host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
- if (family) {
- *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
- }
- if (model) {
- *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
- }
- if (stepping) {
- *stepping = eax & 0x0F;
- }
-}
-
/* CPU class name definitions: */
/* Return type name for a given CPU model name
@@ -1632,10 +1600,6 @@ static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
}
-typedef struct PropValue {
- const char *prop, *value;
-} PropValue;
-
typedef struct X86CPUVersionDefinition {
X86CPUVersion version;
const char *alias;
@@ -4132,32 +4096,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
};
-/* KVM-specific features that are automatically added/removed
- * from all CPU models when KVM is enabled.
- */
-static PropValue kvm_default_props[] = {
- { "kvmclock", "on" },
- { "kvm-nopiodelay", "on" },
- { "kvm-asyncpf", "on" },
- { "kvm-steal-time", "on" },
- { "kvm-pv-eoi", "on" },
- { "kvmclock-stable-bit", "on" },
- { "x2apic", "on" },
- { "kvm-msi-ext-dest-id", "off" },
- { "acpi", "off" },
- { "monitor", "off" },
- { "svm", "off" },
- { NULL, NULL },
-};
-
-/* TCG-specific defaults that override all CPU models when using TCG
- */
-static PropValue tcg_default_props[] = {
- { "vme", "off" },
- { NULL, NULL },
-};
-
-
/*
* We resolve CPU model aliases using -v1 when using "-machine
* none", but this is just for compatibility while libvirt isn't
@@ -4199,61 +4137,6 @@ static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
return v;
}
-void x86_cpu_change_kvm_default(const char *prop, const char *value)
-{
- PropValue *pv;
- for (pv = kvm_default_props; pv->prop; pv++) {
- if (!strcmp(pv->prop, prop)) {
- pv->value = value;
- break;
- }
- }
-
- /* It is valid to call this function only for properties that
- * are already present in the kvm_default_props table.
- */
- assert(pv->prop);
-}
-
-static bool lmce_supported(void)
-{
- uint64_t mce_cap = 0;
-
-#ifdef CONFIG_KVM
- if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
- return false;
- }
-#endif
-
- return !!(mce_cap & MCG_LMCE_P);
-}
-
-#define CPUID_MODEL_ID_SZ 48
-
-/**
- * cpu_x86_fill_model_id:
- * Get CPUID model ID string from host CPU.
- *
- * @str should have at least CPUID_MODEL_ID_SZ bytes
- *
- * The function does NOT add a null terminator to the string
- * automatically.
- */
-static int cpu_x86_fill_model_id(char *str)
-{
- uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
- int i;
-
- for (i = 0; i < 3; i++) {
- host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
- memcpy(str + i * 16 + 0, &eax, 4);
- memcpy(str + i * 16 + 4, &ebx, 4);
- memcpy(str + i * 16 + 8, &ecx, 4);
- memcpy(str + i * 16 + 12, &edx, 4);
- }
- return 0;
-}
-
static Property max_x86_cpu_properties[] = {
DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
@@ -4276,62 +4159,25 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
static void max_x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
- CPUX86State *env = &cpu->env;
- KVMState *s = kvm_state;
/* We can't fill the features array here because we don't know yet if
* "migratable" is true or false.
*/
cpu->max_features = true;
-
- if (accel_uses_host_cpuid()) {
- char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
- char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
- int family, model, stepping;
-
- host_vendor_fms(vendor, &family, &model, &stepping);
- cpu_x86_fill_model_id(model_id);
-
- object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
- object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
- object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
- object_property_set_int(OBJECT(cpu), "stepping", stepping,
- &error_abort);
- object_property_set_str(OBJECT(cpu), "model-id", model_id,
- &error_abort);
-
- if (kvm_enabled()) {
- env->cpuid_min_level =
- kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
- env->cpuid_min_xlevel =
- kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
- env->cpuid_min_xlevel2 =
- kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
- } else {
- env->cpuid_min_level =
- hvf_get_supported_cpuid(0x0, 0, R_EAX);
- env->cpuid_min_xlevel =
- hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
- env->cpuid_min_xlevel2 =
- hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
- }
-
- if (lmce_supported()) {
- object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
- }
- object_property_set_bool(OBJECT(cpu), "host-phys-bits", true, &error_abort);
- } else {
- object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
- &error_abort);
- object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
- object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
- object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
- object_property_set_str(OBJECT(cpu), "model-id",
- "QEMU TCG CPU version " QEMU_HW_VERSION,
- &error_abort);
- }
-
object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
+
+ /*
+ * these defaults are used for TCG and all other accelerators
+ * besides KVM and HVF, which overwrite these values
+ */
+ object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
+ &error_abort);
+ object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
+ object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
+ object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
+ object_property_set_str(OBJECT(cpu), "model-id",
+ "QEMU TCG CPU version " QEMU_HW_VERSION,
+ &error_abort);
}
static const TypeInfo max_x86_cpu_type_info = {
@@ -4341,31 +4187,6 @@ static const TypeInfo max_x86_cpu_type_info = {
.class_init = max_x86_cpu_class_init,
};
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
-{
- X86CPUClass *xcc = X86_CPU_CLASS(oc);
-
- xcc->host_cpuid_required = true;
- xcc->ordering = 8;
-
-#if defined(CONFIG_KVM)
- xcc->model_description =
- "KVM processor with all supported host features ";
-#elif defined(CONFIG_HVF)
- xcc->model_description =
- "HVF processor with all supported host features ";
-#endif
-}
-
-static const TypeInfo host_x86_cpu_type_info = {
- .name = X86_CPU_TYPE_NAME("host"),
- .parent = X86_CPU_TYPE_NAME("max"),
- .class_init = host_x86_cpu_class_init,
-};
-
-#endif
-
static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
{
assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
@@ -5087,7 +4908,7 @@ static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
return r;
}
-static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
+void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
{
PropValue *pv;
for (pv = props; pv->prop; pv++) {
@@ -5134,8 +4955,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
{
X86CPUDefinition *def = model->cpudef;
CPUX86State *env = &cpu->env;
- const char *vendor;
- char host_vendor[CPUID_VENDOR_SZ + 1];
FeatureWord w;
/*NOTE: any property set by this function should be returned by
@@ -5162,20 +4981,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
/* legacy-cache defaults to 'off' if CPU model provides cache info */
cpu->legacy_cache = !def->cache_info;
- /* Special cases not set in the X86CPUDefinition structs: */
- /* TODO: in-kernel irqchip for hvf */
- if (kvm_enabled()) {
- if (!kvm_irqchip_in_kernel()) {
- x86_cpu_change_kvm_default("x2apic", "off");
- } else if (kvm_irqchip_is_split() && kvm_enable_x2apic()) {
- x86_cpu_change_kvm_default("kvm-msi-ext-dest-id", "on");
- }
-
- x86_cpu_apply_props(cpu, kvm_default_props);
- } else if (tcg_enabled()) {
- x86_cpu_apply_props(cpu, tcg_default_props);
- }
-
env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
/* sysenter isn't supported in compatibility mode on AMD,
@@ -5185,15 +4990,12 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
* KVM's sysenter/syscall emulation in compatibility mode and
* when doing cross vendor migration
*/
- vendor = def->vendor;
- if (accel_uses_host_cpuid()) {
- uint32_t ebx = 0, ecx = 0, edx = 0;
- host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
- x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
- vendor = host_vendor;
- }
- object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
+ /*
+ * vendor property is set here but then overloaded with the
+ * host cpu vendor for KVM and HVF.
+ */
+ object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
x86_cpu_apply_version_props(cpu, model);
@@ -6223,53 +6025,12 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
apic_mmio_map_once = true;
}
}
-
-static void x86_cpu_machine_done(Notifier *n, void *unused)
-{
- X86CPU *cpu = container_of(n, X86CPU, machine_done);
- MemoryRegion *smram =
- (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
-
- if (smram) {
- cpu->smram = g_new(MemoryRegion, 1);
- memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
- smram, 0, 4 * GiB);
- memory_region_set_enabled(cpu->smram, true);
- memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
- }
-}
#else
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
{
}
#endif
-/* Note: Only safe for use on x86(-64) hosts */
-static uint32_t x86_host_phys_bits(void)
-{
- uint32_t eax;
- uint32_t host_phys_bits;
-
- host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
- if (eax >= 0x80000008) {
- host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
- /* Note: According to AMD doc 25481 rev 2.34 they have a field
- * at 23:16 that can specify a maximum physical address bits for
- * the guest that can override this value; but I've not seen
- * anything with that set.
- */
- host_phys_bits = eax & 0xff;
- } else {
- /* It's an odd 64 bit machine that doesn't have the leaf for
- * physical address bits; fall back to 36 that's most older
- * Intel.
- */
- host_phys_bits = 36;
- }
-
- return host_phys_bits;
-}
-
static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
{
if (*min < value) {
@@ -6581,33 +6342,22 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu)
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
+ CPUClass *cc = CPU_GET_CLASS(cs);
X86CPU *cpu = X86_CPU(dev);
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
CPUX86State *env = &cpu->env;
Error *local_err = NULL;
static bool ht_warned;
- if (xcc->host_cpuid_required) {
- if (!accel_uses_host_cpuid()) {
- g_autofree char *name = x86_cpu_class_get_model_name(xcc);
- error_setg(&local_err, "CPU model '%s' requires KVM", name);
- goto out;
- }
+ /* The accelerator realizefn needs to be called first. */
+ if (cc->accel_cpu) {
+ cc->accel_cpu->cpu_realizefn(cs, errp);
}
- if (cpu->max_features && accel_uses_host_cpuid()) {
- if (enable_cpu_pm) {
- host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
- &cpu->mwait.ecx, &cpu->mwait.edx);
- env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
- if (kvm_enabled() && kvm_has_waitpkg()) {
- env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
- }
- }
- if (kvm_enabled() && cpu->ucode_rev == 0) {
- cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
- MSR_IA32_UCODE_REV);
- }
+ if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
+ g_autofree char *name = x86_cpu_class_get_model_name(xcc);
+ error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
+ goto out;
}
if (cpu->ucode_rev == 0) {
@@ -6659,39 +6409,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
* consumer AMD devices but nothing else.
*/
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
- if (accel_uses_host_cpuid()) {
- uint32_t host_phys_bits = x86_host_phys_bits();
- static bool warned;
-
- /* Print a warning if the user set it to a value that's not the
- * host value.
- */
- if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
- !warned) {
- warn_report("Host physical bits (%u)"
- " does not match phys-bits property (%u)",
- host_phys_bits, cpu->phys_bits);
- warned = true;
- }
-
- if (cpu->host_phys_bits) {
- /* The user asked for us to use the host physical bits */
- cpu->phys_bits = host_phys_bits;
- if (cpu->host_phys_bits_limit &&
- cpu->phys_bits > cpu->host_phys_bits_limit) {
- cpu->phys_bits = cpu->host_phys_bits_limit;
- }
- }
-
- if (cpu->phys_bits &&
- (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
- cpu->phys_bits < 32)) {
- error_setg(errp, "phys-bits should be between 32 and %u "
- " (but is %u)",
- TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
- return;
- }
- } else {
+ if (!accel_uses_host_cpuid()) {
if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
error_setg(errp, "TCG only supports phys-bits=%u",
TCG_PHYS_ADDR_BITS);
@@ -6699,8 +6417,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
}
/* 0 means it was not explicitly set by the user (or by machine
- * compat_props or by the host code above). In this case, the default
- * is the value used by TCG (40).
+ * compat_props or by the host code in host-cpu.c).
+ * In this case, the default is the value used by TCG (40).
*/
if (cpu->phys_bits == 0) {
cpu->phys_bits = TCG_PHYS_ADDR_BITS;
@@ -6772,33 +6490,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
mce_init(cpu);
-#ifndef CONFIG_USER_ONLY
- if (tcg_enabled()) {
- cpu->cpu_as_mem = g_new(MemoryRegion, 1);
- cpu->cpu_as_root = g_new(MemoryRegion, 1);
-
- /* Outer container... */
- memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
- memory_region_set_enabled(cpu->cpu_as_root, true);
-
- /* ... with two regions inside: normal system memory with low
- * priority, and...
- */
- memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
- get_system_memory(), 0, ~0ull);
- memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
- memory_region_set_enabled(cpu->cpu_as_mem, true);
-
- cs->num_ases = 2;
- cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
- cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
-
- /* ... SMRAM with higher priority, linked from /machine/smram. */
- cpu->machine_done.notify = x86_cpu_machine_done;
- qemu_add_machine_init_done_notifier(&cpu->machine_done);
- }
-#endif
-
qemu_init_vcpu(cs);
/*
@@ -6998,6 +6689,8 @@ static void x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
+ CPUClass *cc = CPU_CLASS(xcc);
+
CPUX86State *env = &cpu->env;
env->nr_dies = 1;
@@ -7045,6 +6738,11 @@ static void x86_cpu_initfn(Object *obj)
if (xcc->model) {
x86_cpu_load_model(cpu, xcc->model);
}
+
+ /* if required, do the accelerator-specific cpu initialization */
+ if (cc->accel_cpu) {
+ cc->accel_cpu->cpu_instance_init(CPU(obj));
+ }
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
@@ -7302,11 +7000,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
cc->has_work = x86_cpu_has_work;
-
-#ifdef CONFIG_TCG
- tcg_cpu_common_class_init(cc);
-#endif /* CONFIG_TCG */
-
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
cc->gdb_read_register = x86_cpu_gdb_read_register;
@@ -7417,9 +7110,6 @@ static void x86_cpu_register_types(void)
}
type_register_static(&max_x86_cpu_type_info);
type_register_static(&x86_base_cpu_type_info);
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
- type_register_static(&host_x86_cpu_type_info);
-#endif
}
type_init(x86_cpu_register_types)
diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c
new file mode 100644
index 0000000000..3fceb3d431
--- /dev/null
+++ b/target/i386/host-cpu.c
@@ -0,0 +1,201 @@
+/*
+ * x86 host CPU functions, and "host" cpu type initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "host-cpu.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+
+/* Note: Only safe for use on x86(-64) hosts */
+static uint32_t host_cpu_phys_bits(void)
+{
+ uint32_t eax;
+ uint32_t host_phys_bits;
+
+ host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
+ if (eax >= 0x80000008) {
+ host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
+ /*
+ * Note: According to AMD doc 25481 rev 2.34 they have a field
+ * at 23:16 that can specify a maximum physical address bits for
+ * the guest that can override this value; but I've not seen
+ * anything with that set.
+ */
+ host_phys_bits = eax & 0xff;
+ } else {
+ /*
+ * It's an odd 64 bit machine that doesn't have the leaf for
+ * physical address bits; fall back to 36 that's most older
+ * Intel.
+ */
+ host_phys_bits = 36;
+ }
+
+ return host_phys_bits;
+}
+
+static void host_cpu_enable_cpu_pm(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+
+ host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
+ &cpu->mwait.ecx, &cpu->mwait.edx);
+ env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
+}
+
+static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error **errp)
+{
+ uint32_t host_phys_bits = host_cpu_phys_bits();
+ uint32_t phys_bits = cpu->phys_bits;
+ static bool warned;
+
+ /*
+ * Print a warning if the user set it to a value that's not the
+ * host value.
+ */
+ if (phys_bits != host_phys_bits && phys_bits != 0 &&
+ !warned) {
+ warn_report("Host physical bits (%u)"
+ " does not match phys-bits property (%u)",
+ host_phys_bits, phys_bits);
+ warned = true;
+ }
+
+ if (cpu->host_phys_bits) {
+ /* The user asked for us to use the host physical bits */
+ phys_bits = host_phys_bits;
+ if (cpu->host_phys_bits_limit &&
+ phys_bits > cpu->host_phys_bits_limit) {
+ phys_bits = cpu->host_phys_bits_limit;
+ }
+ }
+
+ if (phys_bits &&
+ (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
+ phys_bits < 32)) {
+ error_setg(errp, "phys-bits should be between 32 and %u "
+ " (but is %u)",
+ TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
+ }
+
+ return phys_bits;
+}
+
+void host_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ if (cpu->max_features && enable_cpu_pm) {
+ host_cpu_enable_cpu_pm(cpu);
+ }
+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
+ cpu->phys_bits = host_cpu_adjust_phys_bits(cpu, errp);
+ }
+}
+
+#define CPUID_MODEL_ID_SZ 48
+/**
+ * cpu_x86_fill_model_id:
+ * Get CPUID model ID string from host CPU.
+ *
+ * @str should have at least CPUID_MODEL_ID_SZ bytes
+ *
+ * The function does NOT add a null terminator to the string
+ * automatically.
+ */
+static int host_cpu_fill_model_id(char *str)
+{
+ uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
+ memcpy(str + i * 16 + 0, &eax, 4);
+ memcpy(str + i * 16 + 4, &ebx, 4);
+ memcpy(str + i * 16 + 8, &ecx, 4);
+ memcpy(str + i * 16 + 12, &edx, 4);
+ }
+ return 0;
+}
+
+void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping)
+{
+ uint32_t eax, ebx, ecx, edx;
+
+ host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
+
+ host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
+ if (family) {
+ *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
+ }
+ if (model) {
+ *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
+ }
+ if (stepping) {
+ *stepping = eax & 0x0F;
+ }
+}
+
+void host_cpu_instance_init(X86CPU *cpu)
+{
+ uint32_t ebx = 0, ecx = 0, edx = 0;
+ char vendor[CPUID_VENDOR_SZ + 1];
+
+ host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
+ x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
+
+ object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
+}
+
+void host_cpu_max_instance_init(X86CPU *cpu)
+{
+ char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
+ char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
+ int family, model, stepping;
+
+ /* Use max host physical address bits if -cpu max option is applied */
+ object_property_set_bool(OBJECT(cpu), "host-phys-bits", true, &error_abort);
+
+ host_cpu_vendor_fms(vendor, &family, &model, &stepping);
+ host_cpu_fill_model_id(model_id);
+
+ object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
+ object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
+ object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
+ object_property_set_int(OBJECT(cpu), "stepping", stepping,
+ &error_abort);
+ object_property_set_str(OBJECT(cpu), "model-id", model_id,
+ &error_abort);
+}
+
+static void host_cpu_class_init(ObjectClass *oc, void *data)
+{
+ X86CPUClass *xcc = X86_CPU_CLASS(oc);
+
+ xcc->host_cpuid_required = true;
+ xcc->ordering = 8;
+ xcc->model_description =
+ g_strdup_printf("processor with all supported host features ");
+}
+
+static const TypeInfo host_cpu_type_info = {
+ .name = X86_CPU_TYPE_NAME("host"),
+ .parent = X86_CPU_TYPE_NAME("max"),
+ .class_init = host_cpu_class_init,
+};
+
+static void host_cpu_type_init(void)
+{
+ type_register_static(&host_cpu_type_info);
+}
+
+type_init(host_cpu_type_init);
diff --git a/target/i386/hvf/hvf-cpu.c b/target/i386/hvf/hvf-cpu.c
new file mode 100644
index 0000000000..d6579571f1
--- /dev/null
+++ b/target/i386/hvf/hvf-cpu.c
@@ -0,0 +1,65 @@
+/*
+ * x86 HVF CPU type initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "host-cpu.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "sysemu/hvf.h"
+#include "hw/core/accel-cpu.h"
+
+static void hvf_cpu_max_instance_init(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+
+ host_cpu_max_instance_init(cpu);
+
+ env->cpuid_min_level =
+ hvf_get_supported_cpuid(0x0, 0, R_EAX);
+ env->cpuid_min_xlevel =
+ hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
+ env->cpuid_min_xlevel2 =
+ hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
+}
+
+static void hvf_cpu_instance_init(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ host_cpu_instance_init(cpu);
+
+ /* Special cases not set in the X86CPUDefinition structs: */
+ /* TODO: in-kernel irqchip for hvf */
+
+ if (cpu->max_features) {
+ hvf_cpu_max_instance_init(cpu);
+ }
+}
+
+static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_realizefn = host_cpu_realizefn;
+ acc->cpu_instance_init = hvf_cpu_instance_init;
+};
+static const TypeInfo hvf_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("hvf"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = hvf_cpu_accel_class_init,
+ .abstract = true,
+};
+static void hvf_cpu_accel_register_types(void)
+{
+ type_register_static(&hvf_cpu_accel_type_info);
+}
+type_init(hvf_cpu_accel_register_types);
diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
new file mode 100644
index 0000000000..78758780ec
--- /dev/null
+++ b/target/i386/kvm/kvm-cpu.c
@@ -0,0 +1,151 @@
+/*
+ * x86 KVM CPU type initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "host-cpu.h"
+#include "kvm-cpu.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+
+#include "kvm_i386.h"
+#include "hw/core/accel-cpu.h"
+
+static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ /*
+ * The realize order is important, since x86_cpu_realize() checks if
+ * nothing else has been set by the user (or by accelerators) in
+ * cpu->ucode_rev and cpu->phys_bits.
+ *
+ * realize order:
+ * kvm_cpu -> host_cpu -> x86_cpu
+ */
+ if (cpu->max_features) {
+ if (enable_cpu_pm && kvm_has_waitpkg()) {
+ env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
+ }
+ if (cpu->ucode_rev == 0) {
+ cpu->ucode_rev =
+ kvm_arch_get_supported_msr_feature(kvm_state,
+ MSR_IA32_UCODE_REV);
+ }
+ }
+ host_cpu_realizefn(cs, errp);
+}
+
+/*
+ * KVM-specific features that are automatically added/removed
+ * from all CPU models when KVM is enabled.
+ */
+static PropValue kvm_default_props[] = {
+ { "kvmclock", "on" },
+ { "kvm-nopiodelay", "on" },
+ { "kvm-asyncpf", "on" },
+ { "kvm-steal-time", "on" },
+ { "kvm-pv-eoi", "on" },
+ { "kvmclock-stable-bit", "on" },
+ { "x2apic", "on" },
+ { "kvm-msi-ext-dest-id", "off" },
+ { "acpi", "off" },
+ { "monitor", "off" },
+ { "svm", "off" },
+ { NULL, NULL },
+};
+
+void x86_cpu_change_kvm_default(const char *prop, const char *value)
+{
+ PropValue *pv;
+ for (pv = kvm_default_props; pv->prop; pv++) {
+ if (!strcmp(pv->prop, prop)) {
+ pv->value = value;
+ break;
+ }
+ }
+
+ /*
+ * It is valid to call this function only for properties that
+ * are already present in the kvm_default_props table.
+ */
+ assert(pv->prop);
+}
+
+static bool lmce_supported(void)
+{
+ uint64_t mce_cap = 0;
+
+ if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
+ return false;
+ }
+ return !!(mce_cap & MCG_LMCE_P);
+}
+
+static void kvm_cpu_max_instance_init(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+ KVMState *s = kvm_state;
+
+ host_cpu_max_instance_init(cpu);
+
+ if (lmce_supported()) {
+ object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
+ }
+
+ env->cpuid_min_level =
+ kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
+ env->cpuid_min_xlevel =
+ kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
+ env->cpuid_min_xlevel2 =
+ kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
+}
+
+static void kvm_cpu_instance_init(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ host_cpu_instance_init(cpu);
+
+ if (!kvm_irqchip_in_kernel()) {
+ x86_cpu_change_kvm_default("x2apic", "off");
+ } else if (kvm_irqchip_is_split() && kvm_enable_x2apic()) {
+ x86_cpu_change_kvm_default("kvm-msi-ext-dest-id", "on");
+ }
+
+ /* Special cases not set in the X86CPUDefinition structs: */
+
+ x86_cpu_apply_props(cpu, kvm_default_props);
+
+ if (cpu->max_features) {
+ kvm_cpu_max_instance_init(cpu);
+ }
+}
+
+static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_realizefn = kvm_cpu_realizefn;
+ acc->cpu_instance_init = kvm_cpu_instance_init;
+}
+static const TypeInfo kvm_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("kvm"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = kvm_cpu_accel_class_init,
+ .abstract = true,
+};
+static void kvm_cpu_accel_register_types(void)
+{
+ type_register_static(&kvm_cpu_accel_type_info);
+}
+type_init(kvm_cpu_accel_register_types);
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 6dc1ee052d..052de11915 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -22,6 +22,7 @@
#include "standard-headers/asm-x86/kvm_para.h"
#include "cpu.h"
+#include "host-cpu.h"
#include "sysemu/sysemu.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm_int.h"
@@ -285,7 +286,7 @@ static bool host_tsx_broken(void)
int family, model, stepping;\
char vendor[CPUID_VENDOR_SZ + 1];
- host_vendor_fms(vendor, &family, &model, &stepping);
+ host_cpu_vendor_fms(vendor, &family, &model, &stepping);
/* Check if we are running on a Haswell host known to have broken TSX */
return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 1e125d2175..1d3d6d1c6a 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -19,13 +19,14 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "tcg-cpu.h"
-#include "exec/exec-all.h"
-#include "sysemu/runstate.h"
#include "helper-tcg.h"
+#include "qemu/accel.h"
+#include "hw/core/accel-cpu.h"
-#if !defined(CONFIG_USER_ONLY)
-#include "hw/i386/apic.h"
+#ifndef CONFIG_USER_ONLY
+#include "sysemu/sysemu.h"
+#include "qemu/units.h"
+#include "exec/address-spaces.h"
#endif
/* Frob eflags into and out of the CPU temporary format. */
@@ -72,7 +73,107 @@ static struct TCGCPUOps x86_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
-void tcg_cpu_common_class_init(CPUClass *cc)
+static void tcg_cpu_class_init(CPUClass *cc)
{
cc->tcg_ops = &x86_tcg_ops;
}
+
+#ifndef CONFIG_USER_ONLY
+
+static void x86_cpu_machine_done(Notifier *n, void *unused)
+{
+ X86CPU *cpu = container_of(n, X86CPU, machine_done);
+ MemoryRegion *smram =
+ (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
+
+ if (smram) {
+ cpu->smram = g_new(MemoryRegion, 1);
+ memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
+ smram, 0, 4 * GiB);
+ memory_region_set_enabled(cpu->smram, true);
+ memory_region_add_subregion_overlap(cpu->cpu_as_root, 0,
+ cpu->smram, 1);
+ }
+}
+
+static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ /*
+ * The realize order is important, since x86_cpu_realize() checks if
+ * nothing else has been set by the user (or by accelerators) in
+ * cpu->ucode_rev and cpu->phys_bits, and the memory regions
+ * initialized here are needed for the vcpu initialization.
+ *
+ * realize order:
+ * tcg_cpu -> host_cpu -> x86_cpu
+ */
+ cpu->cpu_as_mem = g_new(MemoryRegion, 1);
+ cpu->cpu_as_root = g_new(MemoryRegion, 1);
+
+ /* Outer container... */
+ memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
+ memory_region_set_enabled(cpu->cpu_as_root, true);
+
+ /*
+ * ... with two regions inside: normal system memory with low
+ * priority, and...
+ */
+ memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
+ get_system_memory(), 0, ~0ull);
+ memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
+ memory_region_set_enabled(cpu->cpu_as_mem, true);
+
+ cs->num_ases = 2;
+ cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
+ cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
+
+ /* ... SMRAM with higher priority, linked from /machine/smram. */
+ cpu->machine_done.notify = x86_cpu_machine_done;
+ qemu_add_machine_init_done_notifier(&cpu->machine_done);
+}
+
+#else /* CONFIG_USER_ONLY */
+
+static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+{
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+/*
+ * TCG-specific defaults that override all CPU models when using TCG
+ */
+static PropValue tcg_default_props[] = {
+ { "vme", "off" },
+ { NULL, NULL },
+};
+
+static void tcg_cpu_instance_init(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ /* Special cases not set in the X86CPUDefinition structs: */
+ x86_cpu_apply_props(cpu, tcg_default_props);
+}
+
+static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_realizefn = tcg_cpu_realizefn;
+ acc->cpu_class_init = tcg_cpu_class_init;
+ acc->cpu_instance_init = tcg_cpu_instance_init;
+}
+static const TypeInfo tcg_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("tcg"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = tcg_cpu_accel_class_init,
+ .abstract = true,
+};
+static void tcg_cpu_accel_register_types(void)
+{
+ type_register_static(&tcg_cpu_accel_type_info);
+}
+type_init(tcg_cpu_accel_register_types);
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a83b60312..2826a4bfb8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -340,7 +340,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
M: Richard Henderson <richard.henderson@linaro.org>
M: Eduardo Habkost <ehabkost@redhat.com>
S: Maintained
-F: target/i386/
+F: target/i386/tcg/
F: tests/tcg/i386/
F: tests/tcg/x86_64/
F: hw/i386/
diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build
index e9eb5a5da8..d253d5fd10 100644
--- a/target/i386/hvf/meson.build
+++ b/target/i386/hvf/meson.build
@@ -10,4 +10,5 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files(
'x86_mmu.c',
'x86_task.c',
'x86hvf.c',
+ 'hvf-cpu.c',
))
diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build
index 1d66559187..0a533411ca 100644
--- a/target/i386/kvm/meson.build
+++ b/target/i386/kvm/meson.build
@@ -1,3 +1,8 @@
i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
-i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+
+i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files(
+ 'kvm.c',
+ 'kvm-cpu.c',
+))
+
i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))
diff --git a/target/i386/meson.build b/target/i386/meson.build
index c4bf20b319..fd24479590 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -6,7 +6,11 @@ i386_ss.add(files(
'xsave_helper.c',
'cpu-dump.c',
))
-i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
+i386_ss.add(when: 'CONFIG_SEV', if_true: files('host-cpu.c', 'sev.c'), if_false: files('sev-stub.c'))
+
+# x86 cpu type
+i386_ss.add(when: 'CONFIG_KVM', if_true: files('host-cpu.c'))
+i386_ss.add(when: 'CONFIG_HVF', if_true: files('host-cpu.c'))
i386_softmmu_ss = ss.source_set()
i386_softmmu_ss.add(files(
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 20/22] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (18 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 19/22] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 21/22] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn Claudio Fontana
` (2 subsequent siblings)
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
move the call to accel_cpu->cpu_realizefn to the general
cpu_exec_realizefn from target/i386, so it does not need to be
called for every target explicitly as we enable more targets.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
cpu.c | 6 ++++++
target/i386/cpu.c | 20 +++++++-------------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/cpu.c b/cpu.c
index bfbe5a66f9..ba5d272c1e 100644
--- a/cpu.c
+++ b/cpu.c
@@ -36,6 +36,7 @@
#include "sysemu/replay.h"
#include "exec/translate-all.h"
#include "exec/log.h"
+#include "hw/core/accel-cpu.h"
uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;
@@ -130,6 +131,11 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
cpu_list_add(cpu);
+ if (cc->accel_cpu) {
+ /* NB: errp parameter is unused currently */
+ cc->accel_cpu->cpu_realizefn(cpu, errp);
+ }
+
#ifdef CONFIG_TCG
/* NB: errp parameter is unused currently */
if (tcg_enabled()) {
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 56a299ef14..9bfbf19a71 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6342,16 +6342,19 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu)
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
- CPUClass *cc = CPU_GET_CLASS(cs);
X86CPU *cpu = X86_CPU(dev);
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
CPUX86State *env = &cpu->env;
Error *local_err = NULL;
static bool ht_warned;
- /* The accelerator realizefn needs to be called first. */
- if (cc->accel_cpu) {
- cc->accel_cpu->cpu_realizefn(cs, errp);
+ /* Process Hyper-V enlightenments */
+ x86_cpu_hyperv_realize(cpu);
+
+ cpu_exec_realizefn(cs, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
}
if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
@@ -6467,15 +6470,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
env->cache_info_amd.l3_cache = &legacy_l3_cache;
}
- /* Process Hyper-V enlightenments */
- x86_cpu_hyperv_realize(cpu);
-
- cpu_exec_realizefn(cs, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
-
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 21/22] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (19 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 20/22] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-28 9:28 ` [PATCH v14 22/22] accel: introduce new accessor functions Claudio Fontana
2021-01-29 0:22 ` [PATCH v14 00/22] i386 cleanup PART 2 Richard Henderson
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
move the call to qemu_init_vcpu inside cpu_common_realizefn,
so it does not need to be done explicitly in each target cpu.
Despite this, the way cpu realize is done continues to be not ideal;
ideally the cpu_list_add would be done in common_cpu,
and in this case we could avoid even more redundant open coded
additional calls in target/xxx/cpu.c,
but this cannot happen because target cpu code, plugins, etc
now all came to rely on cpu->index
(which is updated in cpu_list_add), since no particular order
was defined previously, so we are stuck with the freak call
order for the target cpu realizefn.
After this patch the target/xxx/cpu.c realizefn body becomes:
void mycpu_realizefn(DeviceState *dev, Error **errp)
{
/* ... */
cpu_exec_realizefn(CPU_STATE(dev), errp);
/* ... anything that needs done pre-qemu_vcpu_init */
xcc->parent_realize(dev, errp); /* does qemu_vcpu_init */
/* ... anything that needs to be done after qemu_vcpu_init */
}
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
hw/core/cpu.c | 2 ++
target/alpha/cpu.c | 5 +----
target/arm/cpu.c | 4 +---
target/avr/cpu.c | 3 +--
target/cris/cpu.c | 2 --
target/hppa/cpu.c | 1 -
target/i386/cpu.c | 5 +----
target/lm32/cpu.c | 3 ---
target/m68k/cpu.c | 2 --
target/microblaze/cpu.c | 9 +++------
target/mips/cpu.c | 2 --
target/moxie/cpu.c | 4 +---
target/nios2/cpu.c | 4 +---
target/openrisc/cpu.c | 4 +---
target/riscv/cpu.c | 8 +++-----
target/rx/cpu.c | 8 +++-----
target/s390x/cpu.c | 3 +--
target/sh4/cpu.c | 2 --
target/sparc/cpu.c | 4 +---
target/tilegx/cpu.c | 2 --
target/tricore/cpu.c | 2 --
target/unicore32/cpu.c | 6 +-----
target/xtensa/cpu.c | 2 --
target/ppc/translate_init.c.inc | 5 ++---
24 files changed, 23 insertions(+), 69 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07d..2d8103167b 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -310,6 +310,8 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
CPUState *cpu = CPU(dev);
Object *machine = qdev_get_machine();
+ qemu_init_vcpu(cpu);
+
/* qdev_get_machine() can return something that's not TYPE_MACHINE
* if this is one of the user-only emulators; in that case there's
* no need to check the ignore_memory_transaction_failures board flag.
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e2..07406d5e38 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -56,18 +56,15 @@ static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
{
- CPUState *cs = CPU(dev);
AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
Error *local_err = NULL;
- cpu_exec_realizefn(cs, &local_err);
+ cpu_exec_realizefn(CPU(dev), &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
- qemu_init_vcpu(cs);
-
acc->parent_realize(dev, errp);
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8790a92797..05521c9ac5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1877,10 +1877,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
}
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
acc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index fa0f8e0e80..b1ffeac72d 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -98,10 +98,9 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
mcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void avr_cpu_set_int(void *opaque, int irq, int level)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fc..da161dae1b 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -135,8 +135,6 @@ static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
ccc->parent_realize(dev, errp);
}
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1f..2724f731b8 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -102,7 +102,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
acc->parent_realize(dev, errp);
#ifndef CONFIG_USER_ONLY
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9bfbf19a71..83c474e270 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6484,8 +6484,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
mce_init(cpu);
- qemu_init_vcpu(cs);
-
+ xcc->parent_realize(dev, &local_err);
/*
* Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
* fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
@@ -6512,8 +6511,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- xcc->parent_realize(dev, &local_err);
-
out:
if (local_err != NULL) {
error_propagate(errp, local_err);
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c23d72874c..3c9987709e 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -133,9 +133,6 @@ static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
-
- qemu_init_vcpu(cs);
-
lcc->parent_realize(dev, errp);
}
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index c6fde8132b..180ad04bd8 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -248,8 +248,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
m68k_cpu_init_gdb(cpu);
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
mcc->parent_realize(dev, errp);
}
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba20203..5ee2c65ada 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -178,15 +178,14 @@ static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
{
- CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
uint8_t version_code = 0;
const char *version;
int i = 0;
Error *local_err = NULL;
- cpu_exec_realizefn(cs, &local_err);
+ cpu_exec_realizefn(CPU(dev), &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
@@ -198,7 +197,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
+ mcc->parent_realize(dev, errp);
version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
for (i = 0; mb_cpu_lookup[i].name && version; i++) {
@@ -264,8 +263,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->cfg.mmu_tlb_access = 3;
cpu->cfg.mmu_zones = 16;
cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
-
- mcc->parent_realize(dev, errp);
}
static void mb_cpu_initfn(Object *obj)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ad163ead62..993a5e0cac 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -624,8 +624,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
mvp_init(env);
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
mcc->parent_realize(dev, errp);
}
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 83bec34d36..f3284e730d 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -66,10 +66,8 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
mcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void moxie_cpu_initfn(Object *obj)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a38..e59ed9e135 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -121,10 +121,8 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
ncc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46..d7877ecfdd 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -105,10 +105,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
occ->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void openrisc_cpu_initfn(Object *obj)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16f1a34238..cc00486b17 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -372,7 +372,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
-static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+static void riscv_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
RISCVCPU *cpu = RISCV_CPU(dev);
@@ -517,10 +517,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_cpu_register_gdb_regs_for_features(cs);
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
mcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void riscv_cpu_init(Object *obj)
@@ -601,7 +599,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
- device_class_set_parent_realize(dc, riscv_cpu_realize,
+ device_class_set_parent_realize(dc, riscv_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26..3dd2e649d3 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -106,7 +106,7 @@ static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
return oc;
}
-static void rx_cpu_realize(DeviceState *dev, Error **errp)
+static void rx_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
@@ -118,10 +118,8 @@ static void rx_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
rcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void rx_cpu_set_irq(void *opaque, int no, int request)
@@ -192,7 +190,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
CPUClass *cc = CPU_CLASS(klass);
RXCPUClass *rcc = RX_CPU_CLASS(klass);
- device_class_set_parent_realize(dc, rx_cpu_realize,
+ device_class_set_parent_realize(dc, rx_cpu_realizefn,
&rcc->parent_realize);
device_class_set_parent_reset(dc, rx_cpu_reset,
&rcc->parent_reset);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d35eb39a1b..303932d51a 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -232,8 +232,8 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
#endif
s390_cpu_gdb_init(cs);
- qemu_init_vcpu(cs);
+ scc->parent_realize(dev, &err);
/*
* KVM requires the initial CPU reset ioctl to be executed on the target
* CPU thread. CPU hotplug under single-threaded TCG will not work with
@@ -246,7 +246,6 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
cpu_reset(cs);
}
- scc->parent_realize(dev, &err);
out:
error_propagate(errp, err);
}
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index a78d283bc8..5ee540c6c5 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -186,8 +186,6 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
scc->parent_realize(dev, errp);
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc8..82ed3c0152 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -739,9 +739,9 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
- Error *local_err = NULL;
SPARCCPU *cpu = SPARC_CPU(dev);
CPUSPARCState *env = &cpu->env;
+ Error *local_err = NULL;
#if defined(CONFIG_USER_ONLY)
if ((env->def.features & CPU_FEATURE_FLOAT)) {
@@ -769,8 +769,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
-
scc->parent_realize(dev, errp);
}
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index d969c2f133..ae490bb9cd 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -93,8 +93,6 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
tcc->parent_realize(dev, errp);
}
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcb..56cae72fa3 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -93,8 +93,6 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
set_feature(env, TRICORE_FEATURE_13);
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
tcc->parent_realize(dev, errp);
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 0258884f84..04fc657ecb 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -84,18 +84,14 @@ static void uc32_any_cpu_initfn(Object *obj)
static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
{
- CPUState *cs = CPU(dev);
UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
Error *local_err = NULL;
- cpu_exec_realizefn(cs, &local_err);
+ cpu_exec_realizefn(CPU(dev), &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
-
- qemu_init_vcpu(cs);
-
ucc->parent_realize(dev, errp);
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e2b2c7a71c..ebe5dc2090 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -153,8 +153,6 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
- qemu_init_vcpu(cs);
-
xcc->parent_realize(dev, errp);
}
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 9867d0a6e4..e99106bc1c 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10093,7 +10093,7 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu)
return 0;
}
-static void ppc_cpu_realize(DeviceState *dev, Error **errp)
+static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
PowerPCCPU *cpu = POWERPC_CPU(dev);
@@ -10143,7 +10143,6 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
pcc->gdb_num_sprs, "power-spr.xml", 0);
#endif
- qemu_init_vcpu(cs);
pcc->parent_realize(dev, errp);
@@ -10850,7 +10849,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
- device_class_set_parent_realize(dc, ppc_cpu_realize,
+ device_class_set_parent_realize(dc, ppc_cpu_realizefn,
&pcc->parent_realize);
device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
&pcc->parent_unrealize);
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v14 22/22] accel: introduce new accessor functions
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (20 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 21/22] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn Claudio Fontana
@ 2021-01-28 9:28 ` Claudio Fontana
2021-01-29 0:22 ` [PATCH v14 00/22] i386 cleanup PART 2 Richard Henderson
22 siblings, 0 replies; 44+ messages in thread
From: Claudio Fontana @ 2021-01-28 9:28 UTC (permalink / raw)
To: Alex Bennée, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, qemu-devel, Roman Bolshakov,
Alistair Francis, Claudio Fontana
avoid open coding the accesses to cpu->accel_cpu interfaces,
and instead introduce:
accel_cpu_instance_init,
accel_cpu_realizefn
to be used by the targets/ initfn code,
and by cpu_exec_realizefn respectively.
Add warnings about the use of target-specific headers.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
include/hw/core/accel-cpu.h | 11 +++++++----
include/qemu/accel.h | 13 +++++++++++++
accel/accel-common.c | 19 +++++++++++++++++++
cpu.c | 6 +-----
target/i386/cpu.c | 9 ++-------
5 files changed, 42 insertions(+), 16 deletions(-)
diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
index 246b3e2fcb..2edecd026a 100644
--- a/include/hw/core/accel-cpu.h
+++ b/include/hw/core/accel-cpu.h
@@ -1,5 +1,6 @@
/*
* Accelerator interface, specializes CPUClass
+ * This header is used only by target-specific code.
*
* Copyright 2020 SUSE LLC
*
@@ -11,10 +12,12 @@
#define ACCEL_CPU_H
/*
- * these defines cannot be in cpu.h, because we are using
- * CPU_RESOLVING_TYPE here.
- * Use this header to define your accelerator-specific
- * cpu-specific accelerator interfaces.
+ * This header is used to define new accelerator-specific target-specific
+ * accelerator cpu subclasses.
+ * It uses CPU_RESOLVING_TYPE, so this is clearly target-specific.
+ *
+ * Do not try to use for any other purpose than the implementation of new
+ * subclasses in target/, or the accel implementation itself in accel/
*/
#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
diff --git a/include/qemu/accel.h b/include/qemu/accel.h
index b9d6d69eb8..da0c8ab523 100644
--- a/include/qemu/accel.h
+++ b/include/qemu/accel.h
@@ -78,4 +78,17 @@ int accel_init_machine(AccelState *accel, MachineState *ms);
void accel_setup_post(MachineState *ms);
#endif /* !CONFIG_USER_ONLY */
+/**
+ * accel_cpu_instance_init:
+ * @cpu: The CPU that needs to do accel-specific object initializations.
+ */
+void accel_cpu_instance_init(CPUState *cpu);
+
+/**
+ * accel_cpu_realizefn:
+ * @cpu: The CPU that needs to call accel-specific cpu realization.
+ * @errp: currently unused.
+ */
+void accel_cpu_realizefn(CPUState *cpu, Error **errp);
+
#endif /* QEMU_ACCEL_H */
diff --git a/accel/accel-common.c b/accel/accel-common.c
index 9901b0531c..0f6fb4fb66 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -89,6 +89,25 @@ void accel_init_interfaces(AccelClass *ac)
accel_init_cpu_interfaces(ac);
}
+void accel_cpu_instance_init(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) {
+ cc->accel_cpu->cpu_instance_init(cpu);
+ }
+}
+
+void accel_cpu_realizefn(CPUState *cpu, Error **errp)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn) {
+ /* NB: errp parameter is unused currently */
+ cc->accel_cpu->cpu_realizefn(cpu, errp);
+ }
+}
+
static const TypeInfo accel_cpu_type = {
.name = TYPE_ACCEL_CPU,
.parent = TYPE_OBJECT,
diff --git a/cpu.c b/cpu.c
index ba5d272c1e..25e6fbfa2c 100644
--- a/cpu.c
+++ b/cpu.c
@@ -130,11 +130,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
CPUClass *cc = CPU_GET_CLASS(cpu);
cpu_list_add(cpu);
-
- if (cc->accel_cpu) {
- /* NB: errp parameter is unused currently */
- cc->accel_cpu->cpu_realizefn(cpu, errp);
- }
+ accel_cpu_realizefn(cpu, errp);
#ifdef CONFIG_TCG
/* NB: errp parameter is unused currently */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 83c474e270..c79123811f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -28,7 +28,6 @@
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
#include "sysemu/hvf.h"
-#include "hw/core/accel-cpu.h"
#include "sysemu/xen.h"
#include "sysemu/whpx.h"
#include "kvm/kvm_i386.h"
@@ -6680,8 +6679,6 @@ static void x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
- CPUClass *cc = CPU_CLASS(xcc);
-
CPUX86State *env = &cpu->env;
env->nr_dies = 1;
@@ -6730,10 +6727,8 @@ static void x86_cpu_initfn(Object *obj)
x86_cpu_load_model(cpu, xcc->model);
}
- /* if required, do the accelerator-specific cpu initialization */
- if (cc->accel_cpu) {
- cc->accel_cpu->cpu_instance_init(CPU(obj));
- }
+ /* if required, do accelerator-specific cpu initializations */
+ accel_cpu_instance_init(CPU(obj));
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
--
2.26.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v14 00/22] i386 cleanup PART 2
2021-01-28 9:27 [PATCH v14 00/22] i386 cleanup PART 2 Claudio Fontana
` (21 preceding siblings ...)
2021-01-28 9:28 ` [PATCH v14 22/22] accel: introduce new accessor functions Claudio Fontana
@ 2021-01-29 0:22 ` Richard Henderson
22 siblings, 0 replies; 44+ messages in thread
From: Richard Henderson @ 2021-01-29 0:22 UTC (permalink / raw)
To: Claudio Fontana, Alex Bennée, Paolo Bonzini,
Philippe Mathieu-Daudé,
Eduardo Habkost, Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Alistair Francis, Roman Bolshakov,
qemu-devel
On 1/27/21 11:27 PM, Claudio Fontana wrote:
> Claudio Fontana (17):
> target/riscv: remove CONFIG_TCG, as it is always TCG
> accel/tcg: split TCG-only code from cpu_exec_realizefn
> target/arm: do not use cc->do_interrupt for KVM directly
> cpu: move cc->do_interrupt to tcg_ops
> cpu: move cc->transaction_failed to tcg_ops
> cpu: move do_unaligned_access to tcg_ops
> physmem: make watchpoint checking code TCG-only
> cpu: move adjust_watchpoint_address to tcg_ops
> cpu: move debug_check_watchpoint to tcg_ops
> cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
> accel: extend AccelState and AccelClass to user-mode
> accel: replace struct CpusAccel with AccelOpsClass
> accel: introduce AccelCPUClass extending CPUClass
> i386: split cpu accelerators from cpu.c, using AccelCPUClass
> cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn
> hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn
> accel: introduce new accessor functions
>
> Eduardo Habkost (5):
> cpu: Introduce TCGCpuOperations struct
> cpu: Move synchronize_from_tb() to tcg_ops
> cpu: Move cpu_exec_* to tcg_ops
> cpu: Move tlb_fill to tcg_ops
> cpu: Move debug_excp_handler to tcg_ops
I'm going to queue the first 18 patches to tcg-next.
With the exception of the minor target/arm do_interrupt change, they clearly
fall into the tcg bucket.
Patch 19, split i386 accelerators, needs more i386 review, and on a host
accelerator I can't test. If I drop that, then patch 20 doesn't apply, so I'll
let the rest of the series go. But at least it'll reduce the size of your
patch load.
r~
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