From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com>,
qemu-ppc <qemu-ppc@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [Qemu-devel] [PATCH] spapr/xive: Mask the EAS when allocating an IRQ
Date: Tue, 13 Aug 2019 18:48:38 +0200 [thread overview]
Message-ID: <43eb577e-27a7-de43-93f5-b4f2ae8f3b70@kaod.org> (raw)
In-Reply-To: <CAFEAcA-OmF+gOmhJjsaRVJVg1DAj5nXQz0rJ6wEFfAht+VSqnQ@mail.gmail.com>
On 13/08/2019 18:46, Peter Maydell wrote:
> On Tue, 13 Aug 2019 at 17:44, Cédric Le Goater <clg@kaod.org> wrote:
>>
>> If an IRQ is allocated and not configured, such as a MSI requested by
>> a PCI driver, it can be saved in its default state and possibly later
>> on restored using the same state. If not initially MASKED, KVM will
>> try to find a matching priority/target tuple for the interrupt and
>> fail to restore the VM because 0/0 is not a valid target.
>>
>> When allocating a IRQ number, the EAS should be set to a sane default :
>> VALID and MASKED.
>>
>> Reported-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>
>> David, this fixes a "virsh save/restore" issue in certain configurations
>> of CPU topology which never showed up before :/
>>
>> Peter, I was busy on a KVM/passthru issue and lacked the time to
>> investigate all ... you decide.
>
> rc5 has been tagged so this is definitely too late for 4.1.
This is nothing too invasive which will be difficult to backport.
Thanks,
C.
next prev parent reply other threads:[~2019-08-13 16:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-13 16:44 [Qemu-devel] [PATCH] spapr/xive: Mask the EAS when allocating an IRQ Cédric Le Goater
2019-08-13 16:46 ` Peter Maydell
2019-08-13 16:48 ` Cédric Le Goater [this message]
2019-08-14 2:36 ` David Gibson
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