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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id 6sm9429797qth.82.2021.03.22.09.55.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Mar 2021 09:55:48 -0700 (PDT) Subject: Re: [PATCH v4 07/17] target/ppc: Disconnect hflags from MSR To: David Gibson References: <20210315184615.1985590-1-richard.henderson@linaro.org> <20210315184615.1985590-8-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <47d0bf1d-b423-4503-645a-0f293eb95b87@linaro.org> Date: Mon, 22 Mar 2021 10:55:46 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ivan Warren , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/21/21 9:52 PM, David Gibson wrote: >> +/* >> + * Bits for env->hflags. >> + * >> + * Most of these bits overlap with corresponding bits in MSR, >> + * but some come from other sources. Be cautious when modifying. > > Yeah.. I'm not sure "be cautious" is enough of a warning. The exact > value of some but not all of these flags must equal that for the > corresponding MSR bits, which is terrifyingly subtle. Fair. How about, for the comment here, "This is validated in hreg_compute_hflags." >> + /* Some bits come straight across from MSR. */ >> + msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | >> + (1 << MSR_DR) | (1 << MSR_IR) | >> + (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); Here, and in every other spot within this function where we manipulate msr_mask, QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); etc. r~