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From: Rashmica Gupta <rashmica.g@gmail.com>
To: clg@kaod.org
Cc: peter.maydell@linaro.org, andrew@aj.id.au, qemu-devel@nongnu.org,
	aik@ozlabs.ru, qemu-arm@nongnu.org, joel@jms.id.au
Subject: Re: [Qemu-devel] [PATCH v5 2/3] aspeed: add a GPIO controller to the SoC
Date: Fri, 16 Aug 2019 17:40:19 +1000
Message-ID: <4d0aad7fa699a82bcbecb532551827c30c4c0f3d.camel@gmail.com> (raw)
In-Reply-To: <20190816073229.22787-3-rashmica.g@gmail.com>

Cédric, this is how I thought changes to the SOC for your aspeed-4.1
branch would look


From 13a07834476fa266c352d9a075b341c483b2edf9 Mon Sep 17 00:00:00 2001
From: Rashmica Gupta <rashmica.g@gmail.com>
Date: Fri, 16 Aug 2019 15:18:22 +1000
Subject: [PATCH] Aspeed SOC changes

---
 include/hw/arm/aspeed_soc.h |  4 +++-
 hw/arm/aspeed_soc.c         | 32 ++++++++++++++++++++++----------
 2 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 8673661de8..f375271d5a 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -28,6 +28,7 @@
 #define ASPEED_WDTS_NUM  3
 #define ASPEED_CPUS_NUM  2
 #define ASPEED_MACS_NUM  2
+#define ASPEED_GPIOS_NUM  2
 
 typedef struct AspeedSoCState {
     /*< private >*/
@@ -48,7 +49,7 @@ typedef struct AspeedSoCState {
     AspeedSDMCState sdmc;
     AspeedWDTState wdt[ASPEED_WDTS_NUM];
     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
-    AspeedGPIOState gpio;
+    AspeedGPIOState gpio[ASPEED_GPIOS_NUM];
 } AspeedSoCState;
 
 #define TYPE_ASPEED_SOC "aspeed-soc"
@@ -61,6 +62,7 @@ typedef struct AspeedSoCInfo {
     uint64_t sram_size;
     int spis_num;
     int wdts_num;
+    int gpios_num;
     const int *irqmap;
     const hwaddr *memmap;
     uint32_t num_cpus;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 7d47647016..414b99c4f3 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -119,6 +119,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
         .sram_size    = 0x8000,
         .spis_num     = 1,
         .wdts_num     = 2,
+        .gpios_num    = 1,
         .irqmap       = aspeed_soc_ast2400_irqmap,
         .memmap       = aspeed_soc_ast2400_memmap,
         .num_cpus     = 1,
@@ -132,6 +133,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
         .irqmap       = aspeed_soc_ast2500_irqmap,
         .memmap       = aspeed_soc_ast2500_memmap,
         .num_cpus     = 1,
+        .gpios_num    = 1,
     },
 };
 
@@ -226,9 +228,15 @@ static void aspeed_soc_init(Object *obj)
     sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s-
>xdma),
                           TYPE_ASPEED_XDMA);
 
-    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
-    sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s-
>gpio),
-                          typename);
+    for (i = 0; i < sc->info->gpios_num; i++) {
+        if (ASPEED_IS_AST2600(sc->info->silicon_rev)) {
+            snprintf(typename, sizeof(typename), "aspeed.gpio%d-%s",
i, socname);
+        } else {
+            snprintf(typename, sizeof(typename), "aspeed.gpio-%s",
socname);
+        }
+        sysbus_init_child_obj(obj, "gpio[*]", OBJECT(&s->gpio[i]),
sizeof(s->gpio[i]),
+                               typename);
+    }
 }
 
 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -410,15 +418,19 @@ static void aspeed_soc_realize(DeviceState *dev,
Error **errp)
                        aspeed_soc_get_irq(s, ASPEED_XDMA));
 
     /* GPIO */
-    object_property_set_bool(OBJECT(&s->gpio), true, "realized",
&err);
-    if (err) {
-        error_propagate(errp, err);
-        return;
+    for (i = 0; i < sc->info->gpios_num; i++) {
+        hwaddr addr =  sc->info->memmap[ASPEED_GPIO] + i * 0x800;
+        object_property_set_bool(OBJECT(&s->gpio[i]), true,
"realized", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, addr);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
+                           aspeed_soc_get_irq(s, ASPEED_GPIO));
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info-
>memmap[ASPEED_GPIO]);
-    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
-                       aspeed_soc_get_irq(s, ASPEED_GPIO));
 }
+
 static Property aspeed_soc_properties[] = {
     DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
     DEFINE_PROP_END_OF_LIST(),
-- 
2.20.1



  reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16  7:32 [Qemu-devel] [PATCH v4 0/3] Add Aspeed GPIO controller model Rashmica Gupta
2019-08-16  7:32 ` [Qemu-devel] [PATCH v5 1/3] hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500 Rashmica Gupta
2019-08-16 15:59   ` Cédric Le Goater
2019-08-16  7:32 ` [Qemu-devel] [PATCH v5 2/3] aspeed: add a GPIO controller to the SoC Rashmica Gupta
2019-08-16  7:40   ` Rashmica Gupta [this message]
2019-08-16 16:07     ` Cédric Le Goater
2019-08-16 16:00   ` Cédric Le Goater
2019-08-16  7:32 ` [Qemu-devel] [PATCH v5 3/3] hw/gpio: Add in AST2600 specific implementation Rashmica Gupta
2019-08-16 16:01   ` Cédric Le Goater
2019-08-16 16:21 ` [Qemu-devel] [PATCH v4 0/3] Add Aspeed GPIO controller model Cédric Le Goater
2019-08-27  1:33   ` Rashmica Gupta

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