From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Eric Auger" <eric.auger@redhat.com>,
"Aaron Lindsay" <aaron@os.amperecomputing.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists
Date: Fri, 14 Feb 2020 12:15:21 -0800 [thread overview]
Message-ID: <4d592ed0-10c3-683b-84d8-cf17a2d491dc@linaro.org> (raw)
In-Reply-To: <20200214175116.9164-11-peter.maydell@linaro.org>
On 2/14/20 9:51 AM, Peter Maydell wrote:
> The AArch32 DBGDIDR defines properties like the number of
> breakpoints, watchpoints and context-matching comparators. On an
> AArch64 CPU, the register may not even exist if AArch32 is not
> supported at EL1.
>
> Currently we hard-code use of DBGDIDR to identify the number of
> breakpoints etc; this works for all our TCG CPUs, but will break if
> we ever add an AArch64-only CPU. We also have an assert() that the
> AArch32 and AArch64 registers match, which currently works only by
> luck for KVM because we don't populate either of these ID registers
> from the KVM vCPU and so they are both zero.
>
> Clean this up so we have functions for finding the number
> of breakpoints, watchpoints and context comparators which look
> in the appropriate ID register.
>
> This allows us to drop the "check that AArch64 and AArch32 agree
> on the number of breakpoints etc" asserts:
> * we no longer look at the AArch32 versions unless that's the
> right place to be looking
> * it's valid to have a CPU (eg AArch64-only) where they don't match
> * we shouldn't have been asserting the validity of ID registers
> in a codepath used with KVM anyway
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 7 +++++++
> target/arm/internals.h | 42 +++++++++++++++++++++++++++++++++++++++
> target/arm/debug_helper.c | 6 +++---
> target/arm/helper.c | 21 +++++---------------
> 4 files changed, 57 insertions(+), 19 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-02-14 20:16 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 17:50 [PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 Peter Maydell
2020-02-14 17:50 ` [PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Peter Maydell
2020-02-14 17:50 ` [PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan Peter Maydell
2020-02-14 20:10 ` Richard Henderson
2020-02-14 17:50 ` [PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Peter Maydell
2020-02-14 17:50 ` [PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test Peter Maydell
2020-02-14 17:51 ` [PATCH v2 05/21] target/arm: Factor out PMU register definitions Peter Maydell
2020-02-14 17:51 ` [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Peter Maydell
2020-02-14 17:51 ` [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Peter Maydell
2020-02-14 17:51 ` [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function Peter Maydell
2020-02-14 17:51 ` [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Peter Maydell
2020-02-14 17:51 ` [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists Peter Maydell
2020-02-14 20:15 ` Richard Henderson [this message]
2020-02-14 17:51 ` [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters Peter Maydell
2020-02-14 20:16 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM Peter Maydell
2020-02-14 20:27 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' Peter Maydell
2020-02-14 17:51 ` [PATCH v2 16/21] target/arm: Correct definition of PMCRDP Peter Maydell
2020-02-14 17:51 ` [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit Peter Maydell
2020-02-14 17:51 ` [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks Peter Maydell
2020-02-14 20:30 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature Peter Maydell
2020-02-14 20:32 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields Peter Maydell
2020-02-14 20:32 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2 Peter Maydell
2020-02-14 20:42 ` Richard Henderson
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