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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id o11sm5720765ejh.55.2020.12.18.10.01.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Dec 2020 10:01:17 -0800 (PST) Subject: Re: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass To: Claudio Fontana , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20201126223218.31480-1-cfontana@suse.de> <20201126223218.31480-11-cfontana@suse.de> <6cbd508c-b24b-3219-3302-196dfefaa8f7@redhat.com> From: Paolo Bonzini Message-ID: <51838c6c-8a44-afef-1acf-b8acb3eada19@redhat.com> Date: Fri, 18 Dec 2020 19:01:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 18/12/20 18:51, Claudio Fontana wrote: > But with things like cris/ for example, > the tcg functions to use are actually versioned per each subclass of TYPE_CRIS_CPU. > > Different tcg_ops need to be used for different subclasses of the CPU_RESOLVING_TYPE. CRIS is not that bad since it's TCG only. You can just make it a field in CRISCPUClass and copy it over to tcg_ops. I think ARM had something similar though, with different do_interrupt implementations for M and A processors. Somebody from Linaro was cleaning it up as part of some BQL work, but it was never merged. But even in that case, do_interrupt is somewhat special for ARM so making it an xxxCPUClass field makes sense. Paolo > So in order to avoid code in the class initialization like this: > > if (version1) { then set the tcg ops for version 1; } > if (version2) { then set the tcg ops for version 2; ...} etc, > > we could define the right tcg op variants corresponding to the cpu variants, so that everything can be matched automatically. > > But I think we'd need to pass explicitly the cpu type in accel_init_cpu_interfaces for this to work.. > we could still in the future call accel_init_cpu_interfaces multiple times, once for each cpu model we want to use. > > Or, we could do something else: we could delay the accel cpu interface initialization and call it in cpu_create(const char *typename), > where typename needs to be known for sure. > > This last option seems kinda attractive, but any ideas?