From: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: philmd@redhat.com, bin.meng@windriver.com,
alistair.francis@wdc.com, palmer@dabbelt.com,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v3 04/21] target/riscv: additional macros to check instruction support
Date: Thu, 21 Oct 2021 18:22:33 +0200 [thread overview]
Message-ID: <546fec4a-6a13-d92d-e9b1-c98550de38c7@univ-grenoble-alpes.fr> (raw)
In-Reply-To: <3cd0ab2a-1261-066c-cd74-6ce226d1d1b0@linaro.org>
Le 20/10/2021 à 16:08, Richard Henderson a écrit :
> On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
>> +
>> +#define REQUIRE_64_OR_128BIT(ctx) do { \
>> + if (get_xl(ctx) == MXL_RV32) { \
>> + return false; \
>> + } \
>> +} while (0)
>
> So... you've left REQUIRE_64BIT accepting RV128, so that means that your current
> REQUIRE_64_OR_128BIT is redundant. Is that intentional?
>
> It does seem like all places that accept RV128 should accept RV64, but perhaps
> that's just your "limited" caveat in the cover letter.
My bad, indeed there is no instruction only required by RV64. "Limited" was
related to the minimal support of the priviledge spec.
> You don't use REQUIRE_32_OR_64BIT at all. Remove it?
It's a bug : some compressed insns are only RV32/RV64 (this is linked to
the other bug in the order in which the insns stand in the insn16.decode
file that you pointed out).
Frédéric
>
>
> r~
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
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next prev parent reply other threads:[~2021-10-21 16:23 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 9:47 [PATCH v3 00/21] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 01/21] memory: change define name for consistency Frédéric Pétrot
2021-10-20 15:07 ` Philippe Mathieu-Daudé
2021-10-19 9:47 ` [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values Frédéric Pétrot
2021-10-19 18:00 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations Frédéric Pétrot
2021-10-19 18:15 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 04/21] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-10-20 14:08 ` Richard Henderson
2021-10-21 16:22 ` Frédéric Pétrot [this message]
2021-10-19 9:47 ` [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot
2021-10-20 14:14 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-10-20 14:44 ` Richard Henderson
2021-10-22 6:06 ` Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-10-20 14:57 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part Frédéric Pétrot
2021-10-20 15:09 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 09/21] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-10-20 15:11 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 10/21] target/riscv: support for 128-bit loads and store Frédéric Pétrot
2021-10-20 17:31 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-10-20 17:47 ` Richard Henderson
2021-10-20 19:18 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-10-20 17:59 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-10-20 19:06 ` Richard Henderson
2021-10-24 22:49 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-10-20 20:15 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 15/21] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-10-20 20:58 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 16/21] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-10-20 21:38 ` Richard Henderson
2021-10-20 23:03 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-10-20 21:47 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-10-20 21:53 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
2021-10-20 22:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs Frédéric Pétrot
2021-10-20 23:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 21/21] target/riscv: support for 128-bit satp Frédéric Pétrot
2021-10-20 23:09 ` Richard Henderson
2021-10-21 11:12 ` Frédéric Pétrot
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