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[81.36.146.213]) by smtp.gmail.com with ESMTPSA id k6sm12413703wri.83.2021.10.18.02.42.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Oct 2021 02:42:43 -0700 (PDT) Message-ID: <549ece11-990f-a19b-5dfe-508e315a6163@amsat.org> Date: Mon, 18 Oct 2021 11:42:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 Subject: Re: [PATCH] via-ide: Avoid expensive operations in irq handler Content-Language: en-US To: BALATON Zoltan , qemu-devel@nongnu.org References: <20211018014059.13E65746353@zero.eik.bme.hu> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20211018014059.13E65746353@zero.eik.bme.hu> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , John Snow , Gerd Hoffmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/18/21 03:36, BALATON Zoltan wrote: > Cache the pointer to PCI function 0 (ISA bridge, that this IDE device > has to use for IRQs) in the PCIIDEState and pass that as the opaque > data for the interrupt handler to eliminate both the need to look up > function 0 at every interrupt and also a QOM type cast of the opaque > pointer as that's also expensive (mainly due to qom-debug being > enabled by default). > > Suggested-by: Philippe Mathieu-Daudé > Signed-off-by: BALATON Zoltan > --- > hw/ide/via.c | 11 ++++++----- > include/hw/ide/pci.h | 1 + > 2 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/hw/ide/via.c b/hw/ide/via.c > index 82def819c4..30566bc409 100644 > --- a/hw/ide/via.c > +++ b/hw/ide/via.c > @@ -104,15 +104,15 @@ static void bmdma_setup_bar(PCIIDEState *d) > > static void via_ide_set_irq(void *opaque, int n, int level) > { > - PCIDevice *d = PCI_DEVICE(opaque); > + PCIIDEState *d = opaque; > > if (level) { > - d->config[0x70 + n * 8] |= 0x80; > + d->parent_obj.config[0x70 + n * 8] |= 0x80; > } else { > - d->config[0x70 + n * 8] &= ~0x80; > + d->parent_obj.config[0x70 + n * 8] &= ~0x80; > } Better not to access parent_obj, so I'd rather keep the previous code as it. The rest is OK, thanks. If you don't want to respin I can fix and take via mips-next. > > - via_isa_set_irq(pci_get_function_0(d), 14 + n, level); > + via_isa_set_irq(d->func0, 14 + n, level); > } > > static void via_ide_reset(DeviceState *dev) > @@ -188,7 +188,8 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) > bmdma_setup_bar(d); > pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); > > - qdev_init_gpio_in(ds, via_ide_set_irq, 2); > + d->func0 = pci_get_function_0(dev); > + qdev_init_gpio_in_named_with_opaque(ds, via_ide_set_irq, d, NULL, 2); > for (i = 0; i < 2; i++) { > ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); > ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i)); > diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h > index d8384e1c42..89d14abf95 100644 > --- a/include/hw/ide/pci.h > +++ b/include/hw/ide/pci.h > @@ -50,6 +50,7 @@ struct PCIIDEState { > IDEBus bus[2]; > BMDMAState bmdma[2]; > uint32_t secondary; /* used only for cmd646 */ > + PCIDevice *func0; /* used only by IDE functions of superio chips */ > MemoryRegion bmdma_bar; > MemoryRegion cmd_bar[2]; > MemoryRegion data_bar[2]; >