From: "Cédric Le Goater" <clg@kaod.org>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH] ppc/pnv: Fix NMI system reset SRR1 value
Date: Thu, 7 May 2020 19:14:57 +0200 [thread overview]
Message-ID: <55ff4f45-4e1f-e0af-7b25-0c197dd41e19@kaod.org> (raw)
In-Reply-To: <20200507114824.788942-1-npiggin@gmail.com>
On 5/7/20 1:48 PM, Nicholas Piggin wrote:
> Commit a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the
> SRR1 setting wrong for sresets that hit outside of power-save states.
>
> Fix this, better documenting the source for the bit definitions.
>
> Fixes: a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
We should introduce some defines like the SRR1_WAKE ones in Linux and
cleanup powerpc_reset_wakeup(). This function uses cryptic values.
That can be done later on as a followup.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
>
> Thanks to Cedric for pointing out concerns with a previous MCE patch
> that unearthed this as well. Linux does not actually care what these
> SRR1[42:45] bits look like for non-powersave sresets, but we should
> follow documented behaviour as far as possible.
We should introduce some defines like the SRR1_WAKE ones in Linux and
cleanup powerpc_reset_wakeup(). This function uses cryptic values.
That can be done later on as a followup.
I am currently after a bug which results in a CPU hard lockup because
of a pending interrupt. It occurs on a SMP PowerNV machine when it is
stressed with IO, such as scp of a big file.
I am suspecting more and more an issue with an interrupt being handled
when the CPU is coming out of idle. I haven't seen anything wrong in
the models. Unless this maybe :
/* Pretend to be returning from doze always as we don't lose state */
*msr |= (0x1ull << (63 - 47));
I am not sure how in sync it is with PSSCR.
Thanks,
C.
> hw/ppc/pnv.c | 26 ++++++++++++++++++++------
> 1 file changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index a3b7a8d0ff..1b4748ce6d 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1986,12 +1986,26 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
>
> cpu_synchronize_state(cs);
> ppc_cpu_do_system_reset(cs);
> - /*
> - * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> - * dependent. POWER processors use this for xscom triggered interrupts,
> - * which come from the BMC or NMI IPIs.
> - */
> - env->spr[SPR_SRR1] |= PPC_BIT(43);
> + if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
> + /*
> + * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
> + * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
> + * (PPC_BIT(43)).
> + */
> + if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
> + warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
> + env->spr[SPR_SRR1] |= PPC_BIT(43);
> + }
> + } else {
> + /*
> + * For non-powersave system resets, SRR1[42:45] are defined to be
> + * implementation-dependent. The POWER9 User Manual specifies that
> + * an external (SCOM driven, which may come from a BMC nmi command or
> + * another CPU requesting a NMI IPI) system reset exception should be
> + * 0b0010 (PPC_BIT(44)).
> + */
> + env->spr[SPR_SRR1] |= PPC_BIT(44);
> + }
> }
>
> static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
>
next prev parent reply other threads:[~2020-05-07 17:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-07 11:48 [PATCH] ppc/pnv: Fix NMI system reset SRR1 value Nicholas Piggin
2020-05-07 13:51 ` David Gibson
2020-05-08 8:43 ` Greg Kurz
2020-05-11 1:30 ` David Gibson
2020-05-07 17:14 ` Cédric Le Goater [this message]
2020-05-08 3:43 ` Nicholas Piggin
2020-05-08 14:05 ` Cédric Le Goater
2020-05-08 3:43 ` no-reply
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