From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 2/6] target-arm: Fix handling of SCR.SMD
Date: Mon, 8 Feb 2016 18:40:21 +0300 [thread overview]
Message-ID: <56B8B6E5.1060809@gmail.com> (raw)
In-Reply-To: <1454690704-16233-3-git-send-email-peter.maydell@linaro.org>
On 05.02.2016 19:45, Peter Maydell wrote:
> We weren't quite implementing the handling of SCR.SMD correctly.
> The condition governing whether the SMD bit should apply only
> for NS state is "is EL3 is AArch32", not "is the current EL AArch32".
> Fix the condition, and clarify the comment both to reflect this and
> to expand slightly on what's going on for the v7-no-Virtualization case.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> The bit about forcing SMD to zero confused me, anyway, since I
> expected it to mean "in this function", not elsewhere...
> ---
> target-arm/op_helper.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 313c0f8..4fedae5 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -614,12 +614,14 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
> int cur_el = arm_current_el(env);
> bool secure = arm_is_secure(env);
> bool smd = env->cp15.scr_el3 & SCR_SMD;
> - /* On ARMv8 AArch32, SMD only applies to NS state.
> - * On ARMv7 SMD only applies to NS state and only if EL2 is available.
> - * For ARMv7 non EL2, we force SMD to zero so we don't need to re-check
> - * the EL2 condition here.
> + /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
> + * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
> + * extensions, SMD only applies to NS state.
> + * On ARMv7 without the Virtualization extensions, the SMD bit
> + * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
> + * so we need not special case this here.
> */
> - bool undef = is_a64(env) ? smd : (!secure && smd);
> + bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
>
> if (arm_is_psci_call(cpu, EXCP_SMC)) {
> /* If PSCI is enabled and this looks like a valid PSCI call then
next prev parent reply other threads:[~2016-02-08 15:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-05 16:44 [Qemu-devel] [PATCH 0/6] target-arm: Implement various EL3 traps Peter Maydell
2016-02-05 16:44 ` [Qemu-devel] [PATCH 1/6] target-arm: correct CNTFRQ access rights Peter Maydell
2016-02-08 15:25 ` Sergey Fedorov
2016-02-08 15:30 ` Peter Maydell
2016-02-05 16:45 ` [Qemu-devel] [PATCH 2/6] target-arm: Fix handling of SCR.SMD Peter Maydell
2016-02-08 15:40 ` Sergey Fedorov [this message]
2016-02-05 16:45 ` [Qemu-devel] [PATCH 3/6] target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps Peter Maydell
2016-02-08 15:49 ` [Qemu-devel] [Qemu-arm] " Sergey Fedorov
2016-02-05 16:45 ` [Qemu-devel] [PATCH 4/6] target-arm: Implement MDCR_EL2.TDRA traps Peter Maydell
2016-02-08 15:56 ` Sergey Fedorov
2016-02-05 16:45 ` [Qemu-devel] [PATCH 5/6] target-arm: Implement MDCR_EL2.TDA and MDCR_EL2.TDA traps Peter Maydell
2016-02-08 16:31 ` Sergey Fedorov
2016-02-08 16:38 ` Peter Maydell
2016-02-08 16:44 ` Sergey Fedorov
2016-02-05 16:45 ` [Qemu-devel] [PATCH 6/6] target-arm: Report correct syndrome for FPEXC32_EL2 traps Peter Maydell
2016-02-08 16:40 ` Sergey Fedorov
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