From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTC2W-0008Tn-VU for qemu-devel@nongnu.org; Tue, 09 Feb 2016 12:25:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTC2R-0002jU-Td for qemu-devel@nongnu.org; Tue, 09 Feb 2016 12:25:24 -0500 Received: from mail-pa0-x241.google.com ([2607:f8b0:400e:c03::241]:34545) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTC2R-0002jG-EJ for qemu-devel@nongnu.org; Tue, 09 Feb 2016 12:25:19 -0500 Received: by mail-pa0-x241.google.com with SMTP id yy13so7238284pab.1 for ; Tue, 09 Feb 2016 09:25:19 -0800 (PST) Sender: Richard Henderson References: <1455014403-10742-1-git-send-email-rth@twiddle.net> <1455014403-10742-12-git-send-email-rth@twiddle.net> <20160209165052.GC3678@jhogan-linux.le.imgtec.org> From: Richard Henderson Message-ID: <56BA20F8.7090908@twiddle.net> Date: Wed, 10 Feb 2016 04:25:12 +1100 MIME-Version: 1.0 In-Reply-To: <20160209165052.GC3678@jhogan-linux.le.imgtec.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 11/15] tcg-mips: Use mips64r6 instructions in tcg_out_movi List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: James Hogan Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On 02/10/2016 03:50 AM, James Hogan wrote: > I think ret and 0 are the wrong way around here. You're putting 0 in rs > (the destination register), which causes a seg fault. > > OUT: [size=56] > 0xfff30b0064: lw s1,-8(s0) > 0xfff30b0068: bnezalc zero,s1,0xfff30b0090 > 0xfff30b006c: nop > 0xfff30b0070: j 0xfff0000000 > 0xfff30b0074: nop > 0xfff30b0078: lui s1,0xbfc0 > 0xfff30b007c: ori s1,s1,0x580 > 0xfff30b0080: sd s1,256(s0) > 0xfff30b0084: aluipc zero,0xfeb7 > 0xfff30b0088: j 0xfff30b0034 > 0xfff30b008c: ori v0,v0,0x4010 > 0xfff30b0090: aluipc zero,0xfeb7 > 0xfff30b0094: j 0xfff30b0034 > 0xfff30b0098: ori v0,v0,0x4013 > > Cheers > James > > > >> + } else { >> + TCGReg in = TCG_REG_ZERO; >> + tcg_target_long tmp = (int16_t)arg; >> + >> + /* The R6 manual recommends construction of immediates in >> + order of low to high (ADDI, AUI, DAHI, DATI) in order >> + to simplify hardware recognizing these sequences. */ >> + >> + if (tmp) { >> + tcg_out_opc_imm(s, OPC_ADDIU, ret, in, tmp); >> + in = ret; >> + } >> + arg = (arg - tmp) >> 16; >> + tmp = (int16_t)arg; >> + >> + /* Note that DAHI and DATI only have one register operand, >> + and are thus we must put a zero low part in place. Also >> + note that we already eliminated simple 32-bit constants >> + so we know this must happen. */ >> + if (tmp || in != ret) { >> + tcg_out_opc_imm(s, OPC_AUI, ret, in, tmp); >> + } >> + arg = (arg - tmp) >> 16; >> + tmp = (int16_t)arg; >> + >> + if (tmp) { >> + tcg_out_opc_imm(s, OPC_DAHI, ret, 0, tmp); >> + } >> + arg = (arg - tmp) >> 16; >> + tcg_debug_assert(arg == (int16_t)arg); >> + >> + if (arg) { >> + tcg_out_opc_imm(s, OPC_DATI, ret, 0, arg); Same mistake here for DAHI/DATI. r~