From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aVnTG-0007Yg-JW for qemu-devel@nongnu.org; Tue, 16 Feb 2016 16:47:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aVnTD-0006fl-A9 for qemu-devel@nongnu.org; Tue, 16 Feb 2016 16:47:46 -0500 Received: from zose-mta02.web4all.fr ([185.49.20.43]:45867) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aVnTD-0006ed-3N for qemu-devel@nongnu.org; Tue, 16 Feb 2016 16:47:43 -0500 References: <4499d69ec1326c07481e9d8178e64b63f9748706.1454967766.git.jcd@tribudubois.net> <56C38B52.7080904@tribudubois.net> From: Jean-Christophe DUBOIS Message-ID: <56C398FA.8010204@tribudubois.net> Date: Tue, 16 Feb 2016 22:47:38 +0100 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers , Peter Crosthwaite Le 16/02/2016 22:06, Peter Maydell a =C3=A9crit : > On 16 February 2016 at 20:49, Jean-Christophe DUBOIS > wrote: >> Le 16/02/2016 16:31, Peter Maydell a =C3=A9crit : >>> On 8 February 2016 at 22:08, Jean-Christophe Dubois >>> wrote: >>>> + object_property_set_bool(OBJECT(&s->cpu[i]), false, >>>> + "has_el3", &error_abort); >>> Do the CPUs in this board really not have EL3 ? >> >> Well the Cortex A9 is certainly able to get to the secure mode. Howeve= r, if >> I enable it (has_el3 set to true), the OS (Linux or Xvisor) will not b= oot. >> Disabling it allow both OS to boot on the emulated i.MX6. >> >> Would you have some idea on the reason for this "hang" during the boot= when >> EL3 is enabled? > How are you booting the OS/hypervisor? Via -kernel or via -bios ? via -kernel ... > Usually if it doesn't boot this is because there's some bit of > boot rom/loader code that runs on the real h/w and isn't being > run in your QEMU setup, that does the initial setup of the h/w > in secure mode. (In particular, if the secure side doesn't set > the GIC interrupts to be NS accessible then things don't work > very well.) Well I guess on real hw uboot is setting things so that everything work=20 thereafter. But here I don't have uboot and I jump directly to Linux ... In QEMU, other Cortex A9 (Versatilepb.c, Exynos, Zynq ...) are also=20 setting has_el3 to false ... JC > > I wouldn't have expected that to be an issue for booting linux > via -kernel though because there we should be booting the kernel > NS and have a hack to configure the GIC appropriately. > > Peter C may remember the details of how this should work > better than me. > > thanks > -- PMM >