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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id a22sm17794578pfk.108.2019.12.06.06.47.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 06:47:07 -0800 (PST) Subject: Re: [PATCH v5 03/22] target/arm: Add MTE system registers To: Peter Maydell References: <20191011134744.2477-1-richard.henderson@linaro.org> <20191011134744.2477-4-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <597e1b27-24df-164e-d289-f8d8bb69f0c3@linaro.org> Date: Fri, 6 Dec 2019 06:47:05 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/3/19 3:48 AM, Peter Maydell wrote: >> + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, >> + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, > > This should trap if HCR_EL2.TID5 is 1 (since we're adding > support for the TID* ID reg trap bits now). Done. > So, aa64_mte_insn_reg here is checking for ID_AA64PFR1_EL1 != 0 > ("instructions accessible at EL0 are implemented") > and aa64_mte is checking for >= 2 ("full implementation"). > I think a couple of brief comments would clarify: Done. > (The other way to arrange this would be to have the 'real' > TCO regdef in mte_reginfo, and separately have "reginfo > if we only have the dummy visible-from-EL0-parts-only > which defines a constant 0 TCO" (and also make the MSR_i > code implement a RAZ/WI for this case, for consistency). Done. I agree this is a better way to treat the EL0-only case... > An implementation that allows the guest to toggle the PSTATE.TCO > bit to no visible effect is architecturally valid, though. ... because this could turn out to be slightly confusing. r~