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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4
Date: Thu, 15 Aug 2019 14:34:55 -0700
Message-ID: <59bed3d7342ef7513a60285e2711c162be5559fc.1565904855.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1565904855.git.alistair.francis@wdc.com>

Update the Hypervisor CSR addresses to match the v0.4 spec.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 target/riscv/cpu_bits.h | 35 ++++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 11f971ad5d..e99834856c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -173,6 +173,24 @@
 #define CSR_SPTBR           0x180
 #define CSR_SATP            0x180
 
+/* Hpervisor CSRs */
+#define CSR_HSTATUS         0x600
+#define CSR_HEDELEG         0x602
+#define CSR_HIDELEG         0x603
+#define CSR_HCOUNTERNEN     0x606
+#define CSR_HGATP           0x680
+
+#if defined(TARGET_RISCV32)
+#define HGATP_MODE           SATP32_MODE
+#define HGATP_VMID           SATP32_ASID
+#define HGATP_PPN            SATP32_PPN
+#endif
+#if defined(TARGET_RISCV64)
+#define HGATP_MODE           SATP64_MODE
+#define HGATP_VMID           SATP64_ASID
+#define HGATP_PPN            SATP64_PPN
+#endif
+
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1
@@ -206,23 +224,6 @@
 #define CSR_DPC             0x7b1
 #define CSR_DSCRATCH        0x7b2
 
-/* Hpervisor CSRs */
-#define CSR_HSTATUS         0xa00
-#define CSR_HEDELEG         0xa02
-#define CSR_HIDELEG         0xa03
-#define CSR_HGATP           0xa80
-
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE           SATP32_MODE
-#define HGATP_ASID           SATP32_ASID
-#define HGATP_PPN            SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE           SATP64_MODE
-#define HGATP_ASID           SATP64_ASID
-#define HGATP_PPN            SATP64_PPN
-#endif
-
 /* Performance Counters */
 #define CSR_MHPMCOUNTER3    0xb03
 #define CSR_MHPMCOUNTER4    0xb04
-- 
2.22.0



  parent reply index

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-15 21:34 [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:34 ` Alistair Francis [this message]
2019-08-16 13:59   ` [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 Bin Meng
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:35 ` [Qemu-devel] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:35 ` [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-23 15:18   ` Alistair Francis
2019-08-15 22:13 ` [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2 no-reply

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