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From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro
Date: Mon, 5 Apr 2021 07:54:42 -0700	[thread overview]
Message-ID: <5d3da671-8916-5d6f-15d8-1a9acca2accb@linaro.org> (raw)
In-Reply-To: <91de8cea886eaef39f8ff51d3962fc9b75ef1a0c.1617393702.git.alistair.francis@wdc.com>

On 4/2/21 1:02 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/cpu_bits.h   | 11 -----------
>   target/riscv/cpu_helper.c | 21 ++++++++++++++++-----
>   2 files changed, 16 insertions(+), 16 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

> @@ -621,9 +626,15 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
>               get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
>               !pmp_violation;
>       } else {
> -        page_fault_exceptions =
> -            get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
> -            !pmp_violation;
> +        if (riscv_cpu_is_32bit(env)) {
> +            page_fault_exceptions =
> +                get_field(env->hgatp, SATP32_MODE) != VM_1_10_MBARE &&
> +                !pmp_violation;
> +        } else {
> +            page_fault_exceptions =
> +                get_field(env->hgatp, SATP64_MODE) != VM_1_10_MBARE &&
> +                !pmp_violation;
> +        }

Looks like you could simplify this to extract the vm in each if branch, then do 
the comparison afterward.

   if (first) {
     vm = ...
   } else if (32bit) {
     vm = ...
   } else {
     vm = ...
   }
   page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;


r~



  reply	other threads:[~2021-04-05 15:21 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-02 20:02 [PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-02 20:02 ` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-05 14:48   ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-05 14:49   ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-05 14:54   ` Richard Henderson [this message]
2021-04-02 20:02 ` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-05 15:10   ` Richard Henderson
2021-04-07 17:11     ` Alistair Francis
2021-04-08 15:20     ` Alistair Francis
2021-04-08 18:51       ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-05 15:14   ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-05 15:15   ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-05 15:15   ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:03 ` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build Alistair Francis
2021-04-06 14:57   ` Richard Henderson

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