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Fri, 16 Jul 2021 09:29:39 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id i13sm1990127pfr.79.2021.07.16.09.29.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jul 2021 09:29:38 -0700 (PDT) Subject: Re: [PATCH for-6.2 05/34] target/arm: Fix mask handling for MVE narrowing operations To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210713133726.26842-1-peter.maydell@linaro.org> <20210713133726.26842-6-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <5fd384a2-1fd0-42b2-6adf-14ace864629f@linaro.org> Date: Fri, 16 Jul 2021 09:29:36 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210713133726.26842-6-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/13/21 6:36 AM, Peter Maydell wrote: > In the MVE helpers for the narrowing operations (DO_VSHRN and > DO_VSHRN_SAT) we were using the wrong bits of the predicate mask for > the 'top' versions of the insn. This is because the loop works over > the double-sized input elements and shifts the predicate mask by that > many bits each time, but when we write out the half-sized output we > must look at the mask bits for whichever half of the element we are > writing to. > > Correct this by shifting the whole mask right by ESIZE bits for the > 'top' insns. This allows us also to simplify the saturation bit > checking (where we had noticed that we needed to look at a different > mask bit for the 'top' insn.) > > Signed-off-by: Peter Maydell > --- > target/arm/mve_helper.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~