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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id o194sm6364018wme.24.2020.10.17.02.06.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 17 Oct 2020 02:06:30 -0700 (PDT) Subject: Re: [RFC PATCH v3] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) To: Richard Henderson , qemu-devel@nongnu.org, Victor Kamensky References: <20201016133317.553068-1-f4bug@amsat.org> <89c6f926-9692-2b8e-617c-6c950bfd1945@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <621b7f92-c37b-1fc0-dff5-a241c2068733@amsat.org> Date: Sat, 17 Oct 2020 11:06:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1 MIME-Version: 1.0 In-Reply-To: <89c6f926-9692-2b8e-617c-6c950bfd1945@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.253, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Purdie , Khem Raj , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/16/20 7:28 PM, Richard Henderson wrote: > On 10/16/20 6:33 AM, Philippe Mathieu-Daudé wrote: >> Per "MIPS32 34K Processor Core Family Software User's Manual, >> Revision 01.13" page 8 in "Joint TLB (JTLB)" section: >> >> "The JTLB is a fully associative TLB cache containing 16, 32, >> or 64-dual-entries mapping up to 128 virtual pages to their >> corresponding physical addresses." >> >> There is no particular reason to restrict the 34Kf core model to >> 16 TLB entries, so raise its config to 64. >> >> This is helpful for other projects, in particular the Yocto Project: >> >> Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit >> MIPS CI loop. It was observed that in this case CI test execution >> time was almost twice longer than 64bit MIPS variant that runs >> under MIPS64R2-generic model. It was investigated and concluded >> that the difference in number of TLBs 16 in 34Kf case vs 64 in >> MIPS64R2-generic is responsible for most of CI real time execution >> difference. Because with 16 TLBs linux user-land trashes TLB more >> and it needs to execute more instructions in TLB refill handler >> calls, as result it runs much longer. >> >> (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) >> >> Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 >> Reported-by: Victor Kamensky >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> v3: KISS >> Supersedes: <20201015224746.540027-1-f4bug@amsat.org> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> target/mips/translate_init.c.inc | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) > > Reviewed-by: Richard Henderson Thanks, applied to mips-next.