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Wed, 19 May 2021 15:47:08 -0700 (PDT) Received: from [172.16.22.144] ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id 5sm168028vkf.48.2021.05.19.15.47.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 May 2021 15:47:07 -0700 (PDT) Subject: Re: [PATCH 00/24] target/ppc: Clean up mmu translation From: Richard Henderson To: David Gibson References: <20210518201146.794854-1-richard.henderson@linaro.org> <7a4c91d4-c813-2803-e5e7-4f8fe6d6f05d@linaro.org> Message-ID: <6bc68cda-a6aa-68c9-2c6f-f7c6ff95b7db@linaro.org> Date: Wed, 19 May 2021 17:47:05 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <7a4c91d4-c813-2803-e5e7-4f8fe6d6f05d@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::933; envelope-from=richard.henderson@linaro.org; helo=mail-ua1-x933.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/19/21 3:37 PM, Richard Henderson wrote: > On 5/18/21 9:52 PM, David Gibson wrote: >> I've applied 1..15, still looking at the rest. > > Please dequeue.  I want to create a new mmu-internal.h, which affects all the > patches from #1. Alternately, don't. I can move the function later, and it may be a while before I can get back to this. Two outstanding bugs: (1) mmu-radix64.c vs hypervisors. You'll not see these unless you run kvm inside of tcg. Basically, all usage of msr_{hv,pr,ir,dr} within ppc_*_xlate is incorrect. We should be pulling these from the 3 bits of mmu_idx, as outlined in the table in hreg_compute_hflags_value. When you start propagating that around, you see that the second-level translation for loading the pte (2 of the 3 calls to ppc_radix64_partition_scoped_xlate) should not be using the mmu_idx related to the user-mode guest access, but should be using the mmu_idx of the kernel/hypervisor that owns the page table. I can't see that mmu-radix64.c has the same problem. I'm not really sure how the second-level translation for hypervisors works there. Is it by the hypervisor altering the hash table as it is loaded? (2) The direct-segment accesses for 6xx and hash32 use ACCESS_* to conditionally reject an mmu access. This is flawed, because we only arrive into these translation routines on the softtlb slow path. If we have an ACCESS_INT and then an ACCESS_FLOAT, the first will load a tlb entry which the second will use to stay on the fast path. There are several possible solutions: (A) Give tlb_set_page size == 1 for direct-segment addresses. This will cause cputlb.c to force all references to the page back through the slow path and through tlb_fill. At which point env->access_type is correct for each access, and we can reject on type. This could be really slow. But since these direct-segment accesses are also uncached, I would expect the guest OS to only be using them for i/o access. Which is already slow, so perhaps the extra trip through tlb_fill isn't noticeable. (B) Use additional mmu_idx. Not ideal, since we wouldn't be sharing softtlb entries for ACCESS_INT and ACCESS_FLOAT and ACCESS_RES for the normal case. But the relevant mmu_models do not have hypervisor support, so we could still fit them in to 8 mmu_idx. We'd probably want to use special code for ACCESS_CACHE and ACCESS_EXT here. (C) Ignore this special case entirely, dropping everything related to env->access_type. The section of code that uses them is all for really old machine types with comments like /* Direct-store segment : absolutely *BUGGY* for now */ which is not encouraging. And short of writing our own test cases we're not likely to have any code to exercise this. r~