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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id g14sm752398wrv.25.2020.10.05.10.19.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Oct 2020 10:19:33 -0700 (PDT) Subject: Re: [PATCH 01/16] hw/core/cpu: Let CPU object have a clock source To: Igor Mammedov References: <20200928171539.788309-1-f4bug@amsat.org> <20200928171539.788309-2-f4bug@amsat.org> <20200930094313.1120a040@redhat.com> <20201005184009.493629b0@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6f6ae858-6c73-a9bf-c0fa-4d40ebc5c4d4@amsat.org> Date: Mon, 5 Oct 2020 19:19:32 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20201005184009.493629b0@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , "qemu-riscv@nongnu.org" , Eduardo Habkost , Paul Burton , "Edgar E . Iglesias" , qemu-devel@nongnu.org, Wainer dos Santos Moschetta , Aleksandar Markovic , qemu-arm , qemu-ppc , Cleber Rosa , Huacai Chen , =?UTF-8?Q?Herv=c3=a9_Poussineau?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/5/20 6:40 PM, Igor Mammedov wrote: > On Wed, 30 Sep 2020 12:16:53 +0200 > Philippe Mathieu-Daudé wrote: > >> +arm/ppc/riscv folks >> >> On 9/30/20 9:43 AM, Igor Mammedov wrote: >>> On Mon, 28 Sep 2020 19:15:24 +0200 >>> Philippe Mathieu-Daudé wrote: >>> >>>> Let CPUState have a clock source (named 'clk') and CPUClass >>>> have a clock_update() callback. The clock can be optionally >>>> set Using qdev_connect_clock_in() from the Clock API. >>>> If the clock changes, the optional clock_update() will be >>>> called. >>> >>> the sole user of it is mips cpu, so question is why >>> you are making it part of generic CPUm instead of >>> MIPSCPUClass/MIPSCPU? >> >> This is a feature of the CPU, regardless its architecture. >> >> I expect the other archs to start using it soon. > > if there aren't any plans to actually to do that, > I'd keep it to MIPS class and generalize later when there is demand. OK will update the patch. > >> >>> >>>> >>>> Signed-off-by: Philippe Mathieu-Daudé >>>> --- >>>> include/hw/core/cpu.h | 5 +++++ >>>> hw/core/cpu.c | 12 ++++++++++++ >>>> 2 files changed, 17 insertions(+) >>>> >>>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h >>>> index 6c34798c8b3..6989d90c193 100644 >>>> --- a/include/hw/core/cpu.h >>>> +++ b/include/hw/core/cpu.h >>>> @@ -31,6 +31,7 @@ >>>> #include "qemu/thread.h" >>>> #include "qemu/plugin.h" >>>> #include "qom/object.h" >>>> +#include "hw/clock.h" >>>> >>>> typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, >>>> void *opaque); >>>> @@ -155,6 +156,7 @@ struct TranslationBlock; >>>> * @disas_set_info: Setup architecture specific components of disassembly info >>>> * @adjust_watchpoint_address: Perform a target-specific adjustment to an >>>> * address before attempting to match it against watchpoints. >>>> + * @clock_update: Callback for input clock changes >>>> * >>>> * Represents a CPU family or model. >>>> */ >>>> @@ -176,6 +178,7 @@ struct CPUClass { >>>> unsigned size, MMUAccessType access_type, >>>> int mmu_idx, MemTxAttrs attrs, >>>> MemTxResult response, uintptr_t retaddr); >>>> + void (*clock_update)(CPUState *cpu); >>>> bool (*virtio_is_big_endian)(CPUState *cpu); >>>> int (*memory_rw_debug)(CPUState *cpu, vaddr addr, >>>> uint8_t *buf, int len, bool is_write); >>>> @@ -316,6 +319,7 @@ struct qemu_work_item; >>>> * QOM parent. >>>> * @nr_cores: Number of cores within this CPU package. >>>> * @nr_threads: Number of threads within this CPU. >>>> + * @clock: this CPU source clock (an output clock of another device) >>>> * @running: #true if CPU is currently running (lockless). >>>> * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; >>>> * valid under cpu_list_lock. >>>> @@ -400,6 +404,7 @@ struct CPUState { >>>> int num_ases; >>>> AddressSpace *as; >>>> MemoryRegion *memory; >>>> + Clock *clock; >>>> >>>> void *env_ptr; /* CPUArchState */ >>>> IcountDecr *icount_decr_ptr; >>>> diff --git a/hw/core/cpu.c b/hw/core/cpu.c >>>> index c55c09f734c..37fcff3ec64 100644 >>>> --- a/hw/core/cpu.c >>>> +++ b/hw/core/cpu.c >>>> @@ -30,6 +30,7 @@ >>>> #include "qemu/qemu-print.h" >>>> #include "sysemu/tcg.h" >>>> #include "hw/boards.h" >>>> +#include "hw/qdev-clock.h" >>>> #include "hw/qdev-properties.h" >>>> #include "trace/trace-root.h" >>>> #include "qemu/plugin.h" >>>> @@ -247,6 +248,16 @@ void cpu_reset(CPUState *cpu) >>>> trace_guest_cpu_reset(cpu); >>>> } >>>> >>>> +static void cpu_clk_update(void *opaque) >>>> +{ >>>> + CPUState *cpu = opaque; >>>> + CPUClass *cc = CPU_GET_CLASS(cpu); >>>> + >>>> + if (cc->clock_update) { >>>> + cc->clock_update(cpu); >>>> + } >>>> +} >>>> + >>>> static void cpu_common_reset(DeviceState *dev) >>>> { >>>> CPUState *cpu = CPU(dev); >>>> @@ -367,6 +378,7 @@ static void cpu_common_initfn(Object *obj) >>>> /* the default value is changed by qemu_init_vcpu() for softmmu */ >>>> cpu->nr_cores = 1; >>>> cpu->nr_threads = 1; >>>> + cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk", cpu_clk_update, cpu); >>>> >>>> qemu_mutex_init(&cpu->work_mutex); >>>> QSIMPLEQ_INIT(&cpu->work_list); >>> >> >