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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id p5sm2161066wrt.79.2019.12.02.22.29.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:29:36 -0800 (PST) Subject: Re: [PATCH v4 38/40] target/arm: Pass more cpu state to arm_excp_unmasked To: Richard Henderson , qemu-devel@nongnu.org References: <20191203022937.1474-1-richard.henderson@linaro.org> <20191203022937.1474-39-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <70810930-85d3-82a0-8917-39277d84c5c6@redhat.com> Date: Tue, 3 Dec 2019 07:29:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203022937.1474-39-richard.henderson@linaro.org> Content-Language: en-US X-MC-Unique: 5oVwH7opNHWbGATtpsmybg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/3/19 3:29 AM, Richard Henderson wrote: > Avoid redundant computation of cpu state by passing it in > from the caller, which has already computed it for itself. >=20 > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=E9 > --- > target/arm/cpu.c | 22 ++++++++++++---------- > 1 file changed, 12 insertions(+), 10 deletions(-) >=20 > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index a36344d4c7..7a1177b883 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s) > } > =20 > static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_id= x, > - unsigned int target_el) > + unsigned int target_el, > + unsigned int cur_el, bool secure, > + uint64_t hcr_el2) > { > CPUARMState *env =3D cs->env_ptr; > - unsigned int cur_el =3D arm_current_el(env); > - bool secure =3D arm_is_secure(env); > bool pstate_unmasked; > int8_t unmasked =3D 0; > - uint64_t hcr_el2; > =20 > /* > * Don't take exceptions if they target a lower EL. > @@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, > return false; > } > =20 > - hcr_el2 =3D arm_hcr_el2_eff(env); > - > switch (excp_idx) { > case EXCP_FIQ: > pstate_unmasked =3D !(env->daif & PSTATE_F); > @@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) > CPUARMState *env =3D cs->env_ptr; > uint32_t cur_el =3D arm_current_el(env); > bool secure =3D arm_is_secure(env); > + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); > uint32_t target_el; > uint32_t excp_idx; > bool ret =3D false; > @@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) > if (interrupt_request & CPU_INTERRUPT_FIQ) { > excp_idx =3D EXCP_FIQ; > target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, sec= ure); > - if (arm_excp_unmasked(cs, excp_idx, target_el)) { > + if (arm_excp_unmasked(cs, excp_idx, target_el, > + cur_el, secure, hcr_el2)) { > cs->exception_index =3D excp_idx; > env->exception.target_el =3D target_el; > cc->do_interrupt(cs); > @@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) > if (interrupt_request & CPU_INTERRUPT_HARD) { > excp_idx =3D EXCP_IRQ; > target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, sec= ure); > - if (arm_excp_unmasked(cs, excp_idx, target_el)) { > + if (arm_excp_unmasked(cs, excp_idx, target_el, > + cur_el, secure, hcr_el2)) { > cs->exception_index =3D excp_idx; > env->exception.target_el =3D target_el; > cc->do_interrupt(cs); > @@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) > if (interrupt_request & CPU_INTERRUPT_VIRQ) { > excp_idx =3D EXCP_VIRQ; > target_el =3D 1; > - if (arm_excp_unmasked(cs, excp_idx, target_el)) { > + if (arm_excp_unmasked(cs, excp_idx, target_el, > + cur_el, secure, hcr_el2)) { > cs->exception_index =3D excp_idx; > env->exception.target_el =3D target_el; > cc->do_interrupt(cs); > @@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) > if (interrupt_request & CPU_INTERRUPT_VFIQ) { > excp_idx =3D EXCP_VFIQ; > target_el =3D 1; > - if (arm_excp_unmasked(cs, excp_idx, target_el)) { > + if (arm_excp_unmasked(cs, excp_idx, target_el, > + cur_el, secure, hcr_el2)) { > cs->exception_index =3D excp_idx; > env->exception.target_el =3D target_el; > cc->do_interrupt(cs); >=20