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Tue, 13 Apr 2021 20:42:54 -0700 (PDT) Received: from [192.168.1.11] ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id np15sm3264801pjb.3.2021.04.13.20.42.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Apr 2021 20:42:53 -0700 (PDT) Subject: Re: [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <058e2779f8bcd25816bc2338a44ab6f1b2d549db.1618356725.git.alistair.francis@wdc.com> From: Richard Henderson Message-ID: <77d3d314-a03e-e081-04c0-a22447fd2658@linaro.org> Date: Tue, 13 Apr 2021 20:42:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <058e2779f8bcd25816bc2338a44ab6f1b2d549db.1618356725.git.alistair.francis@wdc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/13/21 4:34 PM, Alistair Francis wrote: > -#ifndef CONFIG_USER_ONLY > -# ifdef TARGET_RISCV32 > -# define is_32bit(ctx) true > -# else > +#ifdef TARGET_RISCV32 > +# define is_32bit(ctx) true > +#else > static inline bool is_32bit(DisasContext *ctx) > { > - return !(ctx->misa & RV64); > + return (ctx->misa & RV32) == RV32; Why the change here? Also note the previous comment about fixing this to false for TARGET_RISCV64 && CONFIG_USER_ONLY. > static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) > { > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); > + REQUIRE_64BIT(ctx); I think you should always put the 64-bit check first. That way, on TARGET_RISCV32, the entire function folds away. > > - TCGv t0 = tcg_temp_new(); > + TCGv_i64 t0 = tcg_temp_new_i64(); > gen_set_rm(ctx, a->rm); > gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); > - gen_set_gpr(a->rd, t0); > - tcg_temp_free(t0); > + gen_set_gpr(a->rd, (TCGv) t0); So... I really don't like the cast. This is fixable one of two ways. (1) Change the real helper to use target_ulong. (2) Use the gen_helper_* stubs that I talked about in reply to v1. > @@ -390,8 +390,9 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) > { > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); > + REQUIRE_64BIT(ctx); > > - gen_set_gpr(a->rd, cpu_fpr[a->rs1]); > + gen_set_gpr(a->rd, (TCGv) cpu_fpr[a->rs1]); This one's different, and might be worth #ifdef TARGET_RISCV64 gen_set_gpr #else qemu_build_not_reached #endif > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > @@ -303,11 +303,11 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a) > > TCGv t0 = tcg_temp_new(); > > -#if defined(TARGET_RISCV64) > - tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); > -#else > - tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); > -#endif > + if (!is_32bit(ctx)) { > + tcg_gen_ext32s_tl((TCGv) t0, (TCGv) cpu_fpr[a->rs1]); > + } else { > + tcg_gen_extrl_i64_i32((TCGv_i32) t0, cpu_fpr[a->rs1]); > + } I think you should leave this ifdef alone. The ifdef has determined the size of target_ulong and thus the size of TCGv, and thus the correct move to use. If TARGET_RISCV64 and is_32bit, the high bits are ignored; the fact that they happen to be copies of the sign bit is irrelevant. r~