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X-Received-From: 2607:f8b0:4864:20::843 Subject: Re: [Qemu-devel] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/11/19 2:25 AM, liuzhiwei wrote: > diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c > index 12aa3c0..d673fa5 100644 > --- a/linux-user/riscv/cpu_loop.c > +++ b/linux-user/riscv/cpu_loop.c > @@ -41,6 +41,13 @@ void cpu_loop(CPURISCVState *env) > sigcode = 0; > sigaddr = 0; > > + if (env->foflag) { > + if (env->vfp.vl != 0) { > + env->foflag = false; > + env->pc += 4; > + continue; > + } > + } > switch (trapnr) { > case EXCP_INTERRUPT: > /* just indicate that signals should be handled asap */ > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index e32b612..405caf6 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -521,6 +521,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > [PRV_H] = RISCV_EXCP_H_ECALL, > [PRV_M] = RISCV_EXCP_M_ECALL > }; > + if (env->foflag) { > + if (env->vfp.vl != 0) { > + env->foflag = false; > + env->pc += 4; > + return; > + } > + } I renew my objection to this FOFLAG mechanism. I believe, but have no proof, that this will race between different types of interrupts. Once again I present the ARM SVE first-fault helpers as proof that there is another way. Otherwise, all of the same comments from the normal loads apply. r~