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[83.35.24.93]) by smtp.gmail.com with ESMTPSA id t16sm2425898wrx.89.2021.06.28.21.54.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jun 2021 21:54:23 -0700 (PDT) Subject: Re: [PATCH 3/5] hw/pci-host/bonito: Allow PCI config accesses smaller than 32-bit To: BALATON Zoltan References: <20210624202747.1433023-1-f4bug@amsat.org> <20210624202747.1433023-4-f4bug@amsat.org> <10a58f2c-7b8f-fe6c-53c6-cd70b378395a@eik.bme.hu> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7b5a0eb0-d280-a25f-01c1-54f2b3e6ce5f@amsat.org> Date: Tue, 29 Jun 2021 06:54:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <10a58f2c-7b8f-fe6c-53c6-cd70b378395a@eik.bme.hu> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Huacai Chen , qemu-devel@nongnu.org, Wainer dos Santos Moschetta , Cleber Rosa , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/24/21 10:49 PM, BALATON Zoltan wrote: > On Thu, 24 Jun 2021, Philippe Mathieu-Daudé wrote: >> When running the official PMON firmware for the Fuloong 2E, we see >> 8-bit and 16-bit accesses to PCI config space: >> >>  $ qemu-system-mips64el -M fuloong2e -bios pmon_2e.bin \ >>    -trace -trace bonito\* -trace pci_cfg\* >> >>  pci_cfg_write vt82c686b-pm 05:4 @0x90 <- 0xeee1 >>  bonito_spciconf_small_access PCI config address is smaller then >> 32-bit, addr: 0x4d2, size: 2 >>  pci_cfg_write vt82c686b-pm 05:4 @0xd2 <- 0x1 >>  pci_cfg_write vt82c686b-pm 05:4 @0x4 <- 0x1 >>  pci_cfg_write vt82c686b-isa 05:0 @0x4 <- 0x7 >>  bonito_spciconf_small_access PCI config address is smaller then >> 32-bit, addr: 0x81, size: 1 >>  pci_cfg_read vt82c686b-isa 05:0 @0x81 -> 0x0 >>  bonito_spciconf_small_access PCI config address is smaller then >> 32-bit, addr: 0x81, size: 1 >>  pci_cfg_write vt82c686b-isa 05:0 @0x81 <- 0x80 >>  bonito_spciconf_small_access PCI config address is smaller then >> 32-bit, addr: 0x83, size: 1 >>  pci_cfg_write vt82c686b-isa 05:0 @0x83 <- 0x89 >>  bonito_spciconf_small_access PCI config address is smaller then >> 32-bit, addr: 0x85, size: 1 >>  pci_cfg_write vt82c686b-isa 05:0 @0x85 <- 0x3 >>  bonito_spciconf_small_access PCI config address is smaller then >> 32-bit, addr: 0x5a, size: 1 >>  pci_cfg_write vt82c686b-isa 05:0 @0x5a <- 0x7 >>  bonito_spciconf_small_access PCI config address is smaller then >> 32-bit, addr: 0x85, size: 1 >>  pci_cfg_write vt82c686b-isa 05:0 @0x85 <- 0x1 >> >> Also this is what the Linux kernel does since it supports the Bonito >> north bridge: >> https://elixir.bootlin.com/linux/v2.6.15/source/arch/mips/pci/ops-bonito64.c#L85 >> >> >> So it seems safe to assume the datasheet is incomplete or outdated >> regarding the address constraints. >> >> This problem was exposed by commit 911629e6d3773a8adeab48b >> ("vt82c686: Fix SMBus IO base and configuration registers"). >> >> Reported-by: BALATON Zoltan >> Suggested-by: Jiaxun Yang >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/pci-host/bonito.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c >> index 751fdcec689..3c10608c9a2 100644 >> --- a/hw/pci-host/bonito.c >> +++ b/hw/pci-host/bonito.c >> @@ -187,7 +187,7 @@ FIELD(BONGENCFG, PCIQUEUE,      12, 1) >> #define BONITO_PCICONF_FUN_MASK        0x700    /* [10:8] */ >> #define BONITO_PCICONF_FUN_OFFSET      8 >> #define BONITO_PCICONF_REG_MASK_DS     (~3)         /* Per datasheet */ >> -#define BONITO_PCICONF_REG_MASK        0xFC >> +#define BONITO_PCICONF_REG_MASK_HW     0xff         /* As seen on >> hardware */ > > I think we didn't really see it on hardware just inferred this from what > the firmware does. That's a slight difference but may worth noting so > people later don't think this was really tested with real hardware. > Maybe "As seen with PMON"? OK. > Also if this is a loongson thing as was > thought in the thread in December then maybe the #define could be named > that instead of _HW so if somebody wants to reuse this model later ad > Bonito then know that it implements the Loongson version. Bonito64 is what is modelled. This is what I checked from the Linux kernel: https://elixir.bootlin.com/linux/v2.6.15/source/arch/mips/pci/ops-bonito64.c#L85