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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id j5sm4332446edl.42.2021.02.05.10.05.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Feb 2021 10:05:29 -0800 (PST) Subject: Re: [PATCH 00/24] hw/arm: New board model mps3-an524 To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210205170019.25319-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7d4db6f0-1e11-afb1-2b58-2e115a0a2dd0@amsat.org> Date: Fri, 5 Feb 2021 19:05:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.33, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Daniel P . Berrange" , =?UTF-8?Q?Alex_Benn=c3=a9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/5/21 5:59 PM, Peter Maydell wrote: > This patchseries implements a new board model in the mps2/mps3 family, > based on Application Note AN524: > https://developer.arm.com/documentation/dai0524/latest/ > > Like the other MPS models, this board is an FPGA image; the AN524 > image is based on the SSE-200, like the mps2-an521, but it is > for the MPS3 board rather than the MPS2+. The major differences > are QSPI flash and USB (which we don't model), and support for > 2GB of RAM (which we do). Since the MPS3 is very similar to the > MPS2, I've implemented mps3-an524 as a subclass of TYPE_MPS2TZ_MACHINE, > sharing most of the code with mps2-an505 and mps2-an521. > > The motivation for this model is two-fold: > * Linaro's Zephyr team would like it, so they can test their > code targeting the MPS3 on QEMU > * It's a useful stepping-stone towards a future MPS family model > which uses the SSE-300 and Cortex-M55. All the "make various bits > of mps2-tz.c be driven by per-board data structures rather than > hardcoding them" changes will be needed for that future board model. > This way they can be code-reviewed now, rather than making the > future patchseries even bigger (it will be pretty large even so, > because of all the "implement SSE-300 model" patches). > > This model can run the parts of the AN524 selftest image that > would be expected to work, i.e. the ones that don't rely on things > QEMU doesn't implement. Yes selftest are annoying when emulation :) Lot of features important for real hardware but we can happily bypass when emulation. > (The selftest is part of the AN524 > download so it's behind a EULA click-through and we can't put it > into an acceptance test. We might be able to get something > based on Zephyr or Arm TFM.) Wondering about that... If anyone can go/click/accepts the EULA and download artifacts, then I'd like these tests to be committed to the repository, with a comment containing the download link, and the test can use the skipUntil(BLOB_PATH && BLOB_HASH) syntax to assert the binary I downloaded is the same you used for your test. Then I could run locally: $ PATH_TO_EULA_ACCEPTED_ARTIFACTS=~/Private/DL avocado run ... Would it be acceptable? What is missing or should be fixed? Thanks, Phil.