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Mon, 16 Nov 2020 18:51:26 +0000 From: Ashish Kalra To: pbonzini@redhat.com Subject: [PATCH 05/11] exec: add debug version of physical memory read and write API Date: Mon, 16 Nov 2020 18:51:14 +0000 Message-Id: <7f254436d56679b27ba0112c16472831a6a66b49.1605316268.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM5PR19CA0069.namprd19.prod.outlook.com (2603:10b6:3:116::31) To SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ashkalra_ubuntu_server.amd.com (165.204.77.1) by DM5PR19CA0069.namprd19.prod.outlook.com (2603:10b6:3:116::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25 via Frontend Transport; Mon, 16 Nov 2020 18:51:24 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: cca836d4-a569-446e-3b4f-08d88a609eb0 X-MS-TrafficTypeDiagnostic: SA0PR12MB4557: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3173; 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envelope-from=Ashish.Kalra@amd.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/16 13:51:26 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, FORGED_SPF_HELO=1, MSGID_FROM_MTA_HEADER=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, mtosatti@redhat.com, ssg.sos.patches@amd.com, armbru@redhat.com, qemu-devel@nongnu.org, dgilbert@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Brijesh Singh Adds the following new APIs - cpu_physical_memory_read_debug - cpu_physical_memory_write_debug - cpu_physical_memory_rw_debug - ldl_phys_debug - ldq_phys_debug The subsequent patch will make use of the API introduced, to ensure that the page table walks are handled correctly when debugging an SEV guest. Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- include/exec/cpu-common.h | 15 +++++++++++++ softmmu/physmem.c | 47 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 19805ed6db..d2089e6873 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -71,11 +71,26 @@ size_t qemu_ram_pagesize_largest(void); void cpu_physical_memory_rw(hwaddr addr, void *buf, hwaddr len, bool is_write); +void cpu_physical_memory_rw_debug(hwaddr addr, uint8_t *buf, + int len, int is_write); static inline void cpu_physical_memory_read(hwaddr addr, void *buf, hwaddr len) { cpu_physical_memory_rw(addr, buf, len, false); } +static inline void cpu_physical_memory_read_debug(hwaddr addr, + void *buf, int len) +{ + cpu_physical_memory_rw_debug(addr, buf, len, false); +} +static inline void cpu_physical_memory_write_debug(hwaddr addr, + const void *buf, int len) +{ + cpu_physical_memory_rw_debug(addr, (void *)buf, len, true); +} +uint32_t ldl_phys_debug(CPUState *cpu, hwaddr addr); +uint64_t ldq_phys_debug(CPUState *cpu, hwaddr addr); + static inline void cpu_physical_memory_write(hwaddr addr, const void *buf, hwaddr len) { diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 2c08624ca8..6945bd5efe 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -3354,6 +3354,53 @@ inline MemTxResult address_space_write_rom_debug(AddressSpace *as, return MEMTX_OK; } +uint32_t ldl_phys_debug(CPUState *cpu, hwaddr addr) +{ + MemTxAttrs attrs; + int asidx = cpu_asidx_from_attrs(cpu, attrs); + uint32_t val; + + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + debug_ops->read(cpu->cpu_ases[asidx].as, addr, attrs, + (void *) &val, 4); + + return tswap32(val); +} + +uint64_t ldq_phys_debug(CPUState *cpu, hwaddr addr) +{ + MemTxAttrs attrs; + int asidx = cpu_asidx_from_attrs(cpu, attrs); + uint64_t val; + + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + debug_ops->read(cpu->cpu_ases[asidx].as, addr, attrs, + (void *) &val, 8); + return val; +} + +void cpu_physical_memory_rw_debug(hwaddr addr, uint8_t *buf, + int len, int is_write) +{ + MemTxAttrs attrs; + + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + if (is_write) { + debug_ops->write(&address_space_memory, addr, + attrs, buf, len); + } else { + debug_ops->read(&address_space_memory, addr, + attrs, buf, len); + } + +} + int64_t address_space_cache_init(MemoryRegionCache *cache, AddressSpace *as, hwaddr addr, -- 2.17.1