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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id c9sm9767935wmb.33.2021.02.18.15.11.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Feb 2021 15:11:53 -0800 (PST) Subject: Re: [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 To: Richard Henderson , qemu-devel@nongnu.org References: <20210217202036.1724901-1-richard.henderson@linaro.org> <20210217202036.1724901-6-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7f634553-3e1c-2cd6-a712-31c335e79508@amsat.org> Date: Fri, 19 Feb 2021 00:11:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: <20210217202036.1724901-6-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/17/21 9:19 PM, Richard Henderson wrote: > Use explicit casts for ext8u opcodes, and allow truncation > to happen with the store for st8 opcodes. > > Signed-off-by: Richard Henderson > --- > tcg/tci.c | 23 +++++------------------ > 1 file changed, 5 insertions(+), 18 deletions(-) > > diff --git a/tcg/tci.c b/tcg/tci.c > index 1c667537fe..4ade0ccaf9 100644 > --- a/tcg/tci.c > +++ b/tcg/tci.c > @@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) > } > #endif > > -static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) > -{ > - return (uint8_t)tci_read_reg(regs, index); > -} > - > static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) > { > return (uint16_t)tci_read_reg(regs, index); > @@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) > return value; > } > > -/* Read indexed register (8 bit) from bytecode. */ > -static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr) > -{ > - uint8_t value = tci_read_reg8(regs, **tb_ptr); > - *tb_ptr += 1; > - return value; > -} > - > #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 > /* Read indexed register (8 bit signed) from bytecode. */ > static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) > @@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, > tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); > break; > CASE_32_64(st8) > - t0 = tci_read_r8(regs, &tb_ptr); > + t0 = tci_read_r(regs, &tb_ptr); No need for tb_ptr++ here? > t1 = tci_read_r(regs, &tb_ptr); > t2 = tci_read_s32(&tb_ptr); > *(uint8_t *)(t1 + t2) = t0; > @@ -722,8 +709,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, > #if TCG_TARGET_HAS_ext8u_i32 > case INDEX_op_ext8u_i32: > t0 = *tb_ptr++; > - t1 = tci_read_r8(regs, &tb_ptr); > - tci_write_reg(regs, t0, t1); > + t1 = tci_read_r(regs, &tb_ptr); > + tci_write_reg(regs, t0, (uint8_t)t1); > break; > #endif > #if TCG_TARGET_HAS_ext16u_i32 > @@ -916,8 +903,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, > #if TCG_TARGET_HAS_ext8u_i64 > case INDEX_op_ext8u_i64: > t0 = *tb_ptr++; > - t1 = tci_read_r8(regs, &tb_ptr); > - tci_write_reg(regs, t0, t1); > + t1 = tci_read_r(regs, &tb_ptr); > + tci_write_reg(regs, t0, (uint8_t)t1); > break; > #endif > #if TCG_TARGET_HAS_ext8s_i64 >