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[66.91.136.155]) by smtp.gmail.com with ESMTPSA id s7sm746379pjk.22.2020.01.15.13.28.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Jan 2020 13:28:19 -0800 (PST) Subject: Re: Semihosting, arm, riscv, ppc and common code To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Benjamin Herrenschmidt References: <11d88b2741eac3f634d5aed9e3355c974b533f7b.camel@kernel.crashing.org> <87sgkimkma.fsf@linaro.org> <1309ca0ab6405d88cfd949c73130ad0f2af944a6.camel@kernel.crashing.org> <87wo9tkjxz.fsf@linaro.org> From: Richard Henderson Message-ID: <81f25a9e-a52c-ca8d-4d4b-ca36fcee73ed@linaro.org> Date: Wed, 15 Jan 2020 11:28:14 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <87wo9tkjxz.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liviu Ionescu , keithp@keithp.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/15/20 2:01 AM, Alex Bennée wrote: > Hmm, I'm not so sure. QEMU tries to emulate real HW although I > appreciate that is a somewhat loose definition once you get to things > like -M virt and other such SW like abstractions. Is semihosting even > going to be a thing on real RiscV/Power silicon? For risc-v, the odd nop-full semi-hosting call sequence was chosen to work with jtag debuggers on real silicon. As for the rest of the abi, the stuff after the debugger/emulator has gotten control, they did have the opportunity to do better, and did not. r~