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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id z3sm2171060wrs.94.2019.12.02.22.25.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:25:09 -0800 (PST) Subject: Re: [PATCH v4 06/40] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask To: Richard Henderson , qemu-devel@nongnu.org References: <20191203022937.1474-1-richard.henderson@linaro.org> <20191203022937.1474-7-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <82c07397-e462-9408-67eb-09ba089b5f39@redhat.com> Date: Tue, 3 Dec 2019 07:25:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203022937.1474-7-richard.henderson@linaro.org> Content-Language: en-US X-MC-Unique: VQdAVKpdP5-oIKtdqlwQmQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/3/19 3:29 AM, Richard Henderson wrote: > No functional change, but unify code sequences. >=20 > Reviewed-by: Alex Benn=C3=A9e > Signed-off-by: Richard Henderson Easier to review in 2 patches: vae1_tlbmask first, then vmalle1_tlbmask. If you need to respin, the 2 patches are welcome. Regardless: Reviewed-by: Philippe Mathieu-Daud=C3=A9 > --- > target/arm/helper.c | 118 ++++++++++++++------------------------------ > 1 file changed, 37 insertions(+), 81 deletions(-) >=20 > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 731507a82f..0b0130d814 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3890,70 +3890,61 @@ static CPAccessResult aa64_cacheop_access(CPUARMS= tate *env, > * Page D4-1736 (DDI0487A.b) > */ > =20 > +static int vae1_tlbmask(CPUARMState *env) > +{ > + if (arm_is_secure_below_el3(env)) { > + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; > + } else { > + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; > + } > +} > + > static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegI= nfo *ri, > uint64_t value) > { > CPUState *cs =3D env_cpu(env); > - bool sec =3D arm_is_secure_below_el3(env); > + int mask =3D vae1_tlbmask(env); > =20 > - if (sec) { > - tlb_flush_by_mmuidx_all_cpus_synced(cs, > - ARMMMUIdxBit_S1SE1 | > - ARMMMUIdxBit_S1SE0); > - } else { > - tlb_flush_by_mmuidx_all_cpus_synced(cs, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0); > - } > + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); > } > =20 > static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInf= o *ri, > uint64_t value) > { > CPUState *cs =3D env_cpu(env); > + int mask =3D vae1_tlbmask(env); > =20 > if (tlb_force_broadcast(env)) { > tlbi_aa64_vmalle1is_write(env, NULL, value); > return; > } > =20 > + tlb_flush_by_mmuidx(cs, mask); > +} > + > +static int vmalle1_tlbmask(CPUARMState *env) > +{ > + /* > + * Note that the 'ALL' scope must invalidate both stage 1 and > + * stage 2 translations, whereas most other scopes only invalidate > + * stage 1 translations. > + */ > if (arm_is_secure_below_el3(env)) { > - tlb_flush_by_mmuidx(cs, > - ARMMMUIdxBit_S1SE1 | > - ARMMMUIdxBit_S1SE0); > + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; > + } else if (arm_feature(env, ARM_FEATURE_EL2)) { > + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBi= t_S2NS; > } else { > - tlb_flush_by_mmuidx(cs, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0); > + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; > } > } > =20 > static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo = *ri, > uint64_t value) > { > - /* Note that the 'ALL' scope must invalidate both stage 1 and > - * stage 2 translations, whereas most other scopes only invalidate > - * stage 1 translations. > - */ > - ARMCPU *cpu =3D env_archcpu(env); > - CPUState *cs =3D CPU(cpu); > + CPUState *cs =3D env_cpu(env); > + int mask =3D vmalle1_tlbmask(env); > =20 > - if (arm_is_secure_below_el3(env)) { > - tlb_flush_by_mmuidx(cs, > - ARMMMUIdxBit_S1SE1 | > - ARMMMUIdxBit_S1SE0); > - } else { > - if (arm_feature(env, ARM_FEATURE_EL2)) { > - tlb_flush_by_mmuidx(cs, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0 | > - ARMMMUIdxBit_S2NS); > - } else { > - tlb_flush_by_mmuidx(cs, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0); > - } > - } > + tlb_flush_by_mmuidx(cs, mask); > } > =20 > static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo = *ri, > @@ -3977,28 +3968,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *en= v, const ARMCPRegInfo *ri, > static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInf= o *ri, > uint64_t value) > { > - /* Note that the 'ALL' scope must invalidate both stage 1 and > - * stage 2 translations, whereas most other scopes only invalidate > - * stage 1 translations. > - */ > CPUState *cs =3D env_cpu(env); > - bool sec =3D arm_is_secure_below_el3(env); > - bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); > + int mask =3D vmalle1_tlbmask(env); > =20 > - if (sec) { > - tlb_flush_by_mmuidx_all_cpus_synced(cs, > - ARMMMUIdxBit_S1SE1 | > - ARMMMUIdxBit_S1SE0); > - } else if (has_el2) { > - tlb_flush_by_mmuidx_all_cpus_synced(cs, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0 | > - ARMMMUIdxBit_S2NS); > - } else { > - tlb_flush_by_mmuidx_all_cpus_synced(cs, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0); > - } > + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); > } > =20 > static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInf= o *ri, > @@ -4048,20 +4021,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env= , const ARMCPRegInfo *ri, > static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, > uint64_t value) > { > - ARMCPU *cpu =3D env_archcpu(env); > - CPUState *cs =3D CPU(cpu); > - bool sec =3D arm_is_secure_below_el3(env); > + CPUState *cs =3D env_cpu(env); > + int mask =3D vae1_tlbmask(env); > uint64_t pageaddr =3D sextract64(value << 12, 0, 56); > =20 > - if (sec) { > - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, > - ARMMMUIdxBit_S1SE1 | > - ARMMMUIdxBit_S1SE0); > - } else { > - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0); > - } > + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); > } > =20 > static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *= ri, > @@ -4072,8 +4036,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, = const ARMCPRegInfo *ri, > * since we don't support flush-for-specific-ASID-only or > * flush-last-level-only. > */ > - ARMCPU *cpu =3D env_archcpu(env); > - CPUState *cs =3D CPU(cpu); > + CPUState *cs =3D env_cpu(env); > + int mask =3D vae1_tlbmask(env); > uint64_t pageaddr =3D sextract64(value << 12, 0, 56); > =20 > if (tlb_force_broadcast(env)) { > @@ -4081,15 +4045,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env,= const ARMCPRegInfo *ri, > return; > } > =20 > - if (arm_is_secure_below_el3(env)) { > - tlb_flush_page_by_mmuidx(cs, pageaddr, > - ARMMMUIdxBit_S1SE1 | > - ARMMMUIdxBit_S1SE0); > - } else { > - tlb_flush_page_by_mmuidx(cs, pageaddr, > - ARMMMUIdxBit_S12NSE1 | > - ARMMMUIdxBit_S12NSE0); > - } > + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); > } > =20 > static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo= *ri, >=20